3-d planes memory device

Abstract

The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Mem resistors).

What is claimed is: 
     
         1 . A memory device comprising
 (i) one or more bit line areas in the substrate, each bit line area having a width that is greater than 2 CD wide,   (ii) a plurality of layers comprising information storage elements, each such layer comprising a word line area having a width that is greater than 2CD wide, and   (iii) a plurality of vertical conductive posts passing through the plurality of layers, whereby a vertical conductive post passes through a layer at a point proximate to an information storage element.   
     
     
         2 . A memory device comprising
 (i) a plurality of layers comprising information storage elements,   (ii) a plurality of vertical conductive posts passing through the plurality of layers, whereby a vertical conductive post passes through a layer at a point proximate to an information storage element, and   (iii) one or more of the vertical conductive posts have two or more electrical connections, the electrical connections comprising
 (a) a low impedance path that can be switched on or off and 
 (b) a high impedance path that can be biased to one or more voltages. 
   
     
     
         3 . The memory device of  claim 2  whereby a voltage applied through the low impedance path has a polarity opposite that of a voltage applied through the high impedance path relative to a voltage applied to a layer of the plurality of layers. 
     
     
         4 . A method, comprising:
 depositing alternating layers of conductive and insulating materials on a substrate;   depositing a hard mask on top of the alternating layers;   patterning holes into the alternating layers;   lining the holes with a dielectric material;   filing the holes with a conductive material;   planarizing; and   performing nanoimprint lithography.   
     
     
         5 . The method of  claim 4 , wherein the nanoimprinting lithography comprises:
 depositing a polymer material over the planarized conductive material;   etching the polymer material;   etching the conductive material;   removing dielectric material lining the holes; and   depositing conductive material.   
     
     
         6 . The method of  claim 5 , wherein removing dielectric material linking the holes comprises performing an isotropic dielectric etch such that sidewall dielectric material is removed. 
     
     
         7 . The method of  claim 6 , further comprising performing an anisotropic dielectric etch after the isotropic dielectric etch to remove dielectric material surrounding a top of the conductive material, wherein the dielectric material removed is disposed between a top of the conductive material and a corresponding memory layer plane. 
     
     
         8 . The method of  claim 7 , wherein depositing conductive material comprises conformally depositing conductive material into space between a top of each conductive material post and the memory layer plane. 
     
     
         9 . The method of  claim 8 , further comprising isotropically etching the conductive material that coats a wall of the hole above the posts and leaves the conductive material filled into the space. 
     
     
         10 . The method of  claim 9 , filling the holes remaining above the posts with dielectric material. 
     
     
         11 . The method of  claim 10 , wherein the polymer is photoresist. 
     
     
         12 . The method of  claim 11 , wherein the photoresist has a ramp formed therein.