Semiconductor memory devices

Abstract

A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.

1 . A semiconductor memory device, comprising:
 first conductive lines extending in a first direction on a substrate;   second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points;   a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element; and   an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.   
     
     
         2 . The semiconductor memory device as claimed in  claim 1 , wherein the electrode element includes:
 a first electrode to generate heat and to make contact with one of the first and second conductive lines;   a second electrode between the selection element and the data storage element; and   a third electrode making contact with another of the first and the second conductive lines, the first electrode having the contact area smaller than that of the selection element.   
     
     
         3 . The semiconductor memory device as claimed in  claim 2 , wherein the selection element includes an ovonic threshold switch (OTS) and the data storage element includes a phase changeable material. 
     
     
         4 . The semiconductor memory device as claimed in  claim 3 , wherein:
 the first electrode, the selection element, the second electrode, the data storage element, and the third electrode are sequentially stacked on the first conductive line in a trapezoidal shape, and   the cell structure includes a cell recess that is defined by a side surface of the first electrode, a lower surface of the selection element, and an upper surface of the first conductive line, and is filled with the insulation pattern.   
     
     
         5 . The semiconductor memory device as claimed in  claim 3 , wherein:
 the second electrode, the selection element, the first electrode, the data storage element, and the third electrode are sequentially stacked on the first conductive line in a trapezoidal shape, and   the cell structure includes a cell recess that is defined by a side surface of the first electrode, an upper surface of the selection element, and a lower surface of the data storage element, and is filled with the insulation pattern.   
     
     
         6 . A semiconductor memory device, comprising:
 a lower conductive line extending in a first direction on a substrate;   a middle conductive line extending in a second direction over the lower conductive line, the lower and the middle conductive lines crossing each other at a plurality of first cross points, the middle conductive line having a first component line and a second component line having a width greater than that of the first component line;   an upper conductive line extending in the first direction over the middle conductive line, the middle and the upper conductive lines cross each other at a plurality of second cross points;   a plurality of first cell structures positioned at each of the first cross points of the lower conductive line and the first component line, each of the first cell structures having a first data storage element, a first selection element to apply a cell selection signal to the first data storage element and to change a data state of the first data storage element, and a lower electrode element having at least an electrode having a contact area smaller than that of the first selection element; and   a plurality of second cell structures positioned at each of the second cross points of the second component line and the upper conductive line, each of the second cell structures having a second data storage element, a second selection element to apple a cell selection signal to the second data storage element and to change a data state of the second data storage element, and an upper electrode element having at least an electrode with a contact area smaller than that of the second selection element.   
     
     
         7 . The semiconductor memory device as claimed in  claim 6 , wherein the middle conductive line further includes a separation line between the first component line and the second component line, such that the second component line covers a whole upper surface of the separation line, and a side surface of the second component line is continuous and coplanar with a side surface of the separation line, and the first component line partially covers a lower surface of the separation line and a side surface of the first component line is discontinuous with a side surface of the separation line. 
     
     
         8 . The semiconductor memory device as claimed in  claim 7 , wherein the first and the second component lines include a same metal material and the separation line includes a nitride of the metal material of the first and the second component lines. 
     
     
         9 . The semiconductor memory device as claimed in  claim 7 , further comprising:
 a lower insulation pattern insulating the lower conductive line, the first component line, and the first cell structures with one another, such that the first insulation pattern covers a lower surface of the separation line and the side surface of the first component line; and   an upper insulation pattern insulating the upper conductive line, the second component line and the second cell structures with one another, such that the second insulation pattern covers the side surface of the separation line and is connected to the first insulation pattern.   
     
     
         10 . The semiconductor memory device as claimed in  claim 9 , wherein:
 the first cell structure includes a multilayer structure that is stacked on the lower conductive line in a trapezoidal shape and the first component line covers the an upper surface of the multilayer structure in such a configuration that a side surface of the first component line is slanted at a same angle as the trapezoidal shape of the multilayer structure and a side surface of the first cell structure is coplanar with that of the first component line, and   the second cell structure includes a multilayer structure that is stacked on the second component line in a trapezoidal shape and the a side surface of the second component line is slanted at a same angle as the trapezoidal shape of the multilayer structure and a side surface of the second cell structure is coplanar with that of the second component line.   
     
     
         11 . The semiconductor memory device as claimed in  claim 10 , wherein the lower electrode element includes a first lower electrode arranged on the lower conductive line as a heater and having a width smaller than that of the first selection element, a second lower electrode between the first selection element and the first data storage element, and a third lower electrode between the first data storage element and the first component line, and the first cell structure includes a lower cell recess that is defined by a side surface of the first lower electrode, a lower surface of the first selection element and an upper surface of the lower conductive line and is filled with the lower insulation pattern. 
     
     
         12 . The semiconductor memory device as claimed in  claim 11 , wherein the first lower electrode is exchanged with the second lower electrode, such that the first lower electrode is between the first selection element and the first data storage element, and the lower cell recess is defined by the side surface of the first lower electrode, an upper surface of the first selection element, and a lower surface of the first data storage element. 
     
     
         13 . The semiconductor memory device as claimed in  claim 10 , wherein the upper electrode element includes a first upper electrode arranged on the second component line as a heater and having a width smaller than that of the second selection element, a second upper electrode between the second selection element and the second data storage element, and a third upper electrode interposed between the second data storage element and the upper conductive line, and the second cell structure includes an upper cell recess that is defined by a side surface of the first upper electrode, a lower surface of the second selection element and an upper surface of the second component line and is filled with the upper insulation pattern. 
     
     
         14 . The semiconductor memory device as claimed in  claim 13 , wherein the first upper electrode is exchanged with the second upper electrode such that the first upper electrode is interposed between the second selection element and the second data storage element and the upper cell recess is defined by the side surface of the first upper electrode, an upper surface of the second selection element and a lower surface of the second data storage element. 
     
     
         15 . The semiconductor memory device as claimed in  claim 6 , wherein the first and the second selection elements include one of a vertical PN junction diode, a shottky diode, and an ovonic threshold switch (OTS). 
     
     
         16 . The semiconductor memory device as claimed in  claim 15 , wherein the OTS includes any one of arsenic (As), germanium (Ge), selenium (Se), tellurium (Te), silicon (Si), bismuth (Bi), sodium (S), antimony (Sb) and in combinations thereof. 
     
     
         17 . The semiconductor memory device as claimed in  claim 16 , wherein the OTS includes a 6-element material in which selenium (Se) and sodium (S) are combined with a compound of germanium (Ge), silicon (Si), arsenic (As) and tellurium (Te). 
     
     
         18 .- 20 . (canceled) 
     
     
         21 . A semiconductor memory device, comprising:
 first conductive lines extending in a first direction on a substrate;   second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points;   a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element; and   an insulation pattern between adjacent cell structures along each of the first and second direction.   
     
     
         22 . The semiconductor memory device as claimed in  claim 21 , wherein the electrode element includes a first electrode in direct contact with one of the first and second conductive lines,
 the first electrode having the smaller contact area than that of the selection element, and the first electrode to generate heat.   
     
     
         23 . The semiconductor memory device as claimed in  claim 22 , wherein the first electrode contacts the first conductive line, the cell structure has a cell recess that is defined by a side surface of the first electrode, a lower surface of the selection element, and an upper surface of the first conductive line. 
     
     
         24 .- 25 . (canceled)