Non-inverting buck-boost (bob) automatic pass-through mode

Abstract

An apparatus improves efficiency of a non-inverting buck-or-boost regulator by reducing an amount of switching of the buck-or-boost regulator. A high side buck transistor and a high side boost transistor of the buck-or-boost regulator are turned on. A low side buck transistor and a low side boost transistor are turned off. The turning on and turning off short an input voltage node to an output voltage node of the buck-or-boost regulator to prevent switching of the high side buck transistor and the high side boost transistor. The turning on and turning off are based on a voltage difference between the input voltage node and the output voltage node.

1 . A buck-or-boost switching regulator circuit comprising:
 a high side buck transistor coupled to an input voltage node;   a high side boost transistor coupled to an output voltage node;   a low side buck transistor coupled to the high side buck transistor;   a low side boost transistor coupled to the high side boost transistor;   an inductor coupled to the high side buck transistor, the high side boost transistor, the low side buck transistor and the low side boost transistor; and   an analog control loop circuit configured to close the high side buck transistor and the high side boost transistor and open the low side buck transistor and the low side boost transistor to short the input voltage node to the output voltage node to prevent switching, wherein the opening and closing are based at least in part on a voltage difference between the input voltage node and the output voltage node.   
     
     
         2 . The buck-or-boost switching regulator circuit of  claim 1 , in which the analog control loop circuit comprises a pulse width modulation (PWM) based analog control loop. 
     
     
         3 . The buck-or-boost switching regulator circuit of  claim 2 , in which the analog control loop circuit further comprises an error amplifier configured to receive a feedback signal based at least in part on an output voltage at the output voltage node and to generate an error signal based at least in part on the output voltage at the output voltage node relative to a reference voltage. 
     
     
         4 . The buck-or-boost switching regulator circuit of  claim 3 , in which the analog control loop circuit further comprises a comparator configured to compare the error signal with a boost voltage ramp signal and a buck voltage ramp signal to control switching of the buck-or-boost switching regulator circuit. 
     
     
         5 . The buck-or-boost switching regulator circuit of  claim 1 , in which the analog control loop circuit comprises a pulse frequency modulation (PFM) based analog control loop. 
     
     
         6 . The buck-or-boost switching regulator circuit of  claim 5 , in which the analog control loop circuit comprises a first comparator and a second comparator, the first comparator and the second comparator each configured to receive a feedback signal based at least in part on an output voltage at the output voltage node and to generate a first signal and a second signal from the first comparator and the second comparator, respectively, the first comparator and the second comparator coupled to a control device that controls a power stage of a buck-or-boost converter of the buck-or-boost switching regulator circuit. 
     
     
         7 . The buck-or-boost switching regulator circuit of  claim 6 , in which the power stage is controlled by the control device to regulate the output voltage of the buck-or-boost converter into a regulation window based at least in part on the first signal and the second signal. 
     
     
         8 . The buck-or-boost switching regulator circuit of  claim 7 , in which the control device prevents switching when a load current is supplied, the output voltage is within the regulation window and the load current is below a current limit. 
     
     
         9 . A method comprising:
 turning on a high side buck transistor and a high side boost transistor;   turning off a low side buck transistor and a low side boost transistor, the turning on and turning off shorting an input voltage node to an output voltage node; and   preventing switching of the high side buck transistor and the high side boost transistor, wherein the turning on and the turning off are based at least in part on a voltage difference between the input voltage node and the output voltage node.   
     
     
         10 . The method of  claim 9 , further comprising:
 receiving a feedback signal based at least in part on an output voltage; and   generating an error signal based at least in part on the feedback signal relative to a reference voltage.   
     
     
         11 . The method of  claim 10 , further comprising comparing the error signal with a boost voltage ramp signal and a buck voltage ramp signal to control switching of the high side buck transistor, the high side boost transistor, the low side buck transistor, and the low side boost transistor. 
     
     
         12 . The method of  claim 9 , further comprising:
 receiving a feedback signal based at least in part on an output voltage; and   generating, based at least in part on the feedback signal, a first signal and a second signal from a first comparator and a second comparator, respectively, to control a power stage of a buck-or-boost converter.   
     
     
         13 . A buck-or-boost switching regulator circuit comprising:
 a high side buck transistor coupled to an input voltage node;   a high side boost transistor coupled to an output voltage node;   a low side buck transistor coupled to the high side buck transistor,   a low side boost transistor coupled to the high side boost transistor;   an inductor coupled to the high side buck transistor, the high side boost transistor, the low side buck transistor and the low side boost transistor, and   means for closing the high side buck transistor and the high side boost transistor and opening the low side buck transistor and the low side boost transistor to short the input voltage node to the output voltage node to prevent switching, wherein the opening and closing are based at least in part on a voltage difference between the input voltage node and the output voltage node.   
     
     
         14 . The buck-or-boost switching regulator circuit of  claim 13 , in which the opening and closing means is based at least in part on a pulse width modulation (PWM) implementation. 
     
     
         15 . The buck-or-boost switching regulator circuit of  claim 14 , in which the opening and closing means further comprises:
 means for receiving a feedback signal based at least in part on an output voltage at the output voltage node; and   means for generating an error signal based at least in part on the feedback signal relative to a reference voltage.   
     
     
         16 . The buck-or-boost switching regulator circuit of  claim 15 , in which the opening and closing means further comprises:
 means for comparing the error signal with a boost voltage ramp signal and a buck voltage ramp signal to control switching of the buck-or-boost switching regulator circuit.   
     
     
         17 . The buck-or-boost switching regulator circuit of  claim 13 , in which the opening and closing means is based at least in part on a pulse frequency modulation (PFM) implementation. 
     
     
         18 . The buck-or-boost switching regulator circuit of  claim 17 , in which the opening and closing means further comprises:
 means for receiving a feedback signal based at least in part on an output voltage at the output voltage node and generating a first signal and a second signal to control a power stage of a buck-or-boost converter of the buck-or-boost switching regulator circuit.   
     
     
         19 . The buck-or-boost switching regulator circuit of  claim 18 , further comprising means for generating signals to regulate the output voltage of the buck-or-boost converter into a regulation window based at least in part on the first signal and the second signal. 
     
     
         20 . The buck-or-boost switching regulator circuit of  claim 19 , further comprising means for preventing switching when a load current is supplied, the output voltage is within the regulation window and the load current is below a current limit.