Arbiter Based Serialization of Processor System Management Interrupt Events

Abstract

A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

What is claimed is: 
     
         1 . A processor, comprising:
 a core including circuitry to execute instructions; and   circuitry to:
 detect, on the processor, a first system management interrupt (SMI) event of a first SMI event type; 
 direct an indication of the first SMI event to an arbiter that is outside the processor; 
 receive an interrupt signal from the arbiter; 
   an interrupt handler to respond to the interrupt signal, including circuitry to:
 take action in response to detection of the first SMI event, the action to be dependent on the first SMI event type; and 
 effect an indication that the interrupt handler has completed its actions in response to the interrupt signal. 
   
     
     
         2 . The processor of  claim 1 , wherein:
 the processor further comprises circuitry to:
 communicate the interrupt signal to the core; and 
   the core includes circuitry to:
 pause execution of instructions while the interrupt handler responds to the interrupt signal. 
   
     
     
         3 . The processor of  claim 1 , wherein:
 the processor further comprises circuitry to:
 detect, on the processor and prior to receipt of the interrupt signal, a second SMI event of a second SMI event type different from the first SMI event type; and 
 direct an indication of the second SMI event to the arbiter; 
   the interrupt handler further includes circuitry to:
 take action in response to detection of the second SMI event, the action to be dependent on the second SMI event type. 
   
     
     
         4 . The processor of  claim 1 , wherein:
 the interrupt handler further comprises circuitry to:
 determine the first SMI event type. 
   
     
     
         5 . The processor of  claim 1 , wherein:
 the interrupt handler further comprises circuitry to:
 determine that a second SMI event is pending; and 
 take action in response to the second SMI event. 
   
     
     
         6 . The processor of  claim 1 , wherein:
 the arbiter is a component of a controller hub that arbitrates between SMI events that originate on both the processor and on the controller hub; and   the interrupt handler further comprises circuitry to:
 determine that a second SMI event was detected on the controller hub; and 
 take action in response to the second SMI event. 
   
     
     
         7 . The processor of  claim 1 , wherein:
 the arbiter is a component of a controller hub; and   the processor and the controller hub reside in a single integrated circuit package.   
     
     
         8 . A method, comprising, in a processor:
 detecting, on the processor, a first system management interrupt (SMI) event of a first SMI event type;   directing an indication of the first SMI event to a controller hub that is outside the processor;   receiving an interrupt signal from the controller hub;   executing, in response to receiving the interrupt signal, an interrupt handler, including:
 taking action in response to detecting the first SMI event, the action being dependent on the first SMI event type; and 
 setting an indicator on the controller hub to indicate that the interrupt handler has completed its actions in response to the interrupt signal. 
   
     
     
         9 . The method of  claim 8 , wherein:
 the processor includes a core for executing instructions; and   the method further comprises:
 communicating the interrupt signal to the core; and 
 pausing, by the core, execution of instructions while the interrupt handler responds to the interrupt signal. 
   
     
     
         10 . The method of  claim 8 , wherein:
 the method further comprises:
 detecting, on the processor prior to receiving the interrupt signal, a second SMI event of a second SMI event type different from the first SMI event type; and 
 directing an indication of the second SMI event to the controller hub; 
   executing the interrupt handler further includes:
 taking action in response to detecting the second SMI event, the action being dependent on the second SMI event type. 
   
     
     
         11 . The method of  claim 8 , wherein:
 executing the interrupt handler further comprises:
 determining the first SMI event type. 
   
     
     
         12 . The method of  claim 8 , wherein:
 executing the interrupt handler further comprises:
 determining that a second SMI event is pending; and 
 taking action in response to the second SMI event. 
   
     
     
         13 . The method of  claim 8 , wherein:
 the controller hub arbitrates between SMI events that originate on both the processor and on the controller hub; and   executing the interrupt handler further comprises:
 determining that a second SMI event was detected on the controller hub; and 
 taking action in response to the second SMI event. 
   
     
     
         14 . A system, comprising:
 a controller hub; and   a first processor, comprising:
 a core including circuitry to execute instructions; and 
 circuitry to:
 detect a first system management interrupt (SMI) event from a first SMI event source on the first processor; 
 direct an indication of the first SMI event to the controller hub; 
 receive an interrupt signal from the controller hub; 
 
 an interrupt handler to respond to the interrupt signal, including circuitry to:
 take action in response to detection of the first SMI event, the action to be dependent on the source of the first SMI event; and 
 set an indicator on the controller hub to indicate that the interrupt handler has completed its actions in response to the interrupt signal. 
 
   
     
     
         15 . The system of  claim 14 , wherein:
 the first processor further comprises circuitry to:
 communicate the interrupt signal to the core; 
   the core includes circuitry to:
 pause execution of instructions while the interrupt handler responds to the interrupt signal. 
   
     
     
         16 . The system of  claim 14 , wherein:
 the first processor further comprises circuitry to:
 detect, prior to receipt of the interrupt signal, a second SMI event from a second SMI event source on the first processor different from the first SMI event source; and 
 direct an indication of the second SMI event to the controller hub; 
   the interrupt handler further includes circuitry to:
 take action in response to detection of the second SMI event, the action to be dependent on the source of the second SMI event. 
   
     
     
         17 . The system of  claim 14 , wherein:
 the interrupt handler further comprises circuitry to:
 determine that a second SMI event is pending; and 
 take action in response to the second SMI event. 
   
     
     
         18 . The system of  claim 14 , wherein:
 the controller hub comprises:
 a first SMI status bit whose value indicates whether or not an SMI event has been detected for an SMI event source on the first processor; 
 a second SMI status bit whose value indicates whether or not an SMI event has been detected for an SMI event source on the controller hub; 
   the interrupt handler further comprises circuitry to:
 determine, dependent on the second SMI status bit, that a second SMI event was detected on the controller hub; and 
 take action in response to the second SMI event. 
   
     
     
         19 . The system of  claim 14 , wherein:
 the controller hub comprises:
 an end-of-SMI indicator whose value indicates whether or not the interrupt handler has completed its actions in response to an interrupt issued to the first processor by the controller hub; and 
 circuitry to:
 prevent the controller hub from issuing an interrupt to the first processor while the end-of-SMI indicator is false; 
 determine that at least one SMI event is pending; and 
 issue an interrupt to the first processor in response to determining that at least one SMI event is pending and that the end-of-SMI indicator is true, including circuitry to:
 clear the end-of-SMI indicator; and 
 assert the interrupt signal. 
 
 
   
     
     
         20 . The system of  claim 14 , wherein:
 the system further comprises a second processor;   the indication of the first SMI event includes an identifier of the first processor;   the controller hub comprises:
 a first SMI status bit whose value indicates whether or not an SMI event has been detected for an SMI event source on the first processor; and 
 circuitry to determine, dependent on receipt of the indication of the first SMI event and the identifier of the first processor, that the first SMI status bit is to be set.