Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a Chip

Abstract

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

1 .- 20 . (canceled) 
     
     
         21 . A method comprising:
 receiving first analog routing data from at least one processor circuit;   receiving second analog routing data from a programmable logic section comprising a plurality of digital programmable blocks formed in an integrated circuit;   configuring a dynamically or statically reconfigurable analog routing fabric on the integrated circuit according to the first analog routing data and the second analog routing data to selectively enable connections and disconnections between one or more of a plurality of analog circuit blocks and a plurality of input/output (I/O) pins through a plurality of I/O connection circuits corresponding to the plurality of I/O pins; and   configuring the dynamically or statically reconfigurable analog routing fabric to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.   
     
     
         22 . The method of  claim 21 , further comprising:
 configuring the dynamically or statically reconfigurable analog routing fabric to selectively interconnect one or more of the plurality of analog circuit blocks with input/output (I/O) pins in response to analog routing data from a direct memory access (DMA) circuit configured to transfer data between the integrated circuit and a source external to the integrated circuit.   
     
     
         23 . The method of  claim 21 , wherein the plurality of I/O connection circuits comprise at least one of switch circuits configured to provide connections between single fabric points and any of multiple other fabric points and multiplexer circuits configured to provide a single connection between a single fabric point and one of multiple other fabric points. 
     
     
         24 . The method of  claim 21 , further comprising:
 configuring one of the plurality of I/O connection circuits of the dynamically or statically reconfigurable analog routing fabric to selectively connect an I/O pin corresponding to an I/O connection circuit to at least one of a multiplexer (MUX) bus and at least one of a plurality of global buses, wherein the global buses are connectable to the analog circuit blocks through the dynamically or statically reconfigurable analog routing fabric.   
     
     
         25 . The method of  claim 21 , further comprising:
 configuring one of the plurality of I/O connection circuits of the dynamically or statically reconfigurable analog routing fabric to selectively connect a corresponding analog circuit block to any of a plurality of local buses, wherein the local buses are connectable to the I/O pins through the dynamically or statically reconfigurable analog routing fabric.   
     
     
         26 . The method of  claim 21 , wherein the plurality of analog circuit blocks comprises at least two of an analog signal filter, a comparator, a capacitance sensing circuit, a switched capacitor circuit, a digital-to-analog converter, an analog-to-digital converter, an operational amplifier, or a programmable voltage reference. 
     
     
         27 . A system comprising:
 a plurality of external connection pins;   a digital section coupled to a first subset of the plurality of external connection pins, the digital section comprising a processor circuit, a memory circuit and a plurality of digital programmable blocks; and   an analog section coupled to a second subset of the plurality of external connection pins, the analog section comprising a plurality of analog circuit blocks and a dynamically or statically reconfigurable analog routing fabric configured to selectively connect and disconnect one or more of the plurality of analog circuit blocks the second subset of the plurality of external connection pins through a plurality of input/output (I/O) connection circuits in response to first analog routing data received from the processor circuit and second analog routing data received from the plurality of digital programmable blocks, and to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.   
     
     
         28 . The system of  claim 27 , wherein the dynamically or statically reconfigurable analog routing fabric is configured to selectively interconnect one or more of the plurality of analog circuit blocks with the second subset of the external connection pins in response to analog routing data from a direct memory access (DMA) circuit configured to transfer data between the system and a source external to the system. 
     
     
         29 . The system of  claim 27 , wherein the plurality of I/O connection circuits comprise at least one of switch circuits configured to provide connections between single fabric points and any of multiple other fabric points and multiplexer circuits configured to provide a single connection between a single fabric point and one of multiple other fabric points. 
     
     
         30 . The system of  claim 29 , further comprising at least one voltage generation circuit configured to:
 generate at least one switch voltage outside a range of power supply voltages received by the system; and   provide the at least one switch voltage to at least one I/O connection circuit.   
     
     
         31 . The system of  claim 27 , wherein the plurality of I/O connection circuits of the dynamically or statically reconfigurable analog routing fabric are configured to selectively connect an external connection pin corresponding to an I/O connection circuit to at least one of a multiplexer (MUX) bus and at least one of a plurality of global buses, wherein the global buses are connectable to the analog circuit blocks through the dynamically or statically reconfigurable analog routing fabric. 
     
     
         32 . The system of  claim 27 , the plurality of I/O connection circuits of the dynamically or statically reconfigurable analog routing fabric are configured to selectively connect a corresponding analog circuit block to any of a plurality of local buses, wherein the local buses are connectable to the external connection pins through the dynamically or statically reconfigurable analog routing fabric. 
     
     
         33 . The system of  claim 27 , wherein the plurality of analog circuit blocks comprises at least two of an analog signal filter, a comparator, a capacitance sensing circuit, a switched capacitor circuit, a digital-to-analog converter, an analog-to-digital converter, an operational amplifier, or a programmable voltage reference. 
     
     
         34 . A integrated circuit comprising:
 a plurality of input/outputs (I/Os);   a digital section selectively coupled to a first subset of the plurality of I/Os, the digital section comprising a processor circuit, a memory circuit and a plurality of digital programmable blocks; and   an analog section selectively coupled to a second subset of the plurality of I/Os, the analog section comprising a plurality of analog circuit blocks and a dynamically or statically reconfigurable analog routing fabric configured to selectively connect and disconnect one or more of the plurality of analog circuit blocks to the second subset of the plurality of I/Os in response to first analog routing data received from the processor circuit and second analog routing data received from the plurality of digital programmable blocks, and to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.   
     
     
         35 . The integrated circuit of  claim 34 , wherein the dynamically or statically reconfigurable analog routing fabric is configured to selectively interconnect one or more of the plurality of analog circuit blocks with the second subset of the plurality of I/Os in response to analog routing data from a direct memory access (DMA) circuit configured to transfer data between the integrated circuit and a source external to the integrated circuit. 
     
     
         36 . The integrated circuit of  claim 34 , wherein the plurality of I/Os comprise at least one switch circuit configured to provide connections between single fabric points and any of multiple other fabric points and multiplexer circuits configured to provide a single connection between a single fabric point and one of multiple other fabric points. 
     
     
         37 . The integrated circuit of  claim 36 , further comprising at least one voltage generation circuit configured to:
 generate at least one switch voltage outside a range of power supply voltages received by the system; and   provide the at least one switch voltage to at least one I/O.   
     
     
         38 . The integrated circuit of  claim 34 , wherein the second subset of the plurality of I/Os are configured to selectively connect an external connection pin corresponding to an I/O to at least one of a multiplexer (MUX) bus and at least one of a plurality of global buses, wherein the global buses are connectable to the analog circuit blocks through the dynamically or statically reconfigurable analog routing fabric. 
     
     
         39 . The integrated circuit of  claim 34 , wherein the second subset of the plurality of I/Os are configured to selectively connect a corresponding analog circuit block to any of a plurality of local buses, wherein the local buses are connectable to the external connection pins through the dynamically or statically reconfigurable analog routing fabric. 
     
     
         40 . The integrated circuit of  claim 34 , wherein the plurality of analog circuit blocks comprises at least two of an analog signal filter, a comparator, a capacitance sensing circuit, a switched capacitor circuit, a digital-to-analog converter, an analog-to-digital converter, an operational amplifier, or a programmable voltage reference.