Bias circuit for radio-frequency amplifier

Abstract

Bias circuit for radio-frequency amplifier. In some embodiments, an amplifier circuit for radio-frequency applications can includes an amplifying transistor having an input. The amplifier circuit can further include a bias circuit having a first bias path implemented between a supply node and the input to provide a bias signal to the input of the amplifying transistor, and a second bias path implemented between the supply node and the input to provide an additional bias signal to the input of the amplifying transistor under a selected condition. The first bias path can include a first transistor configured to facilitate the bias signal provided to the input of the amplifying transistor, and the second bias path can include a second transistor configured to facilitate the additional bias signal provided to the input of the amplifying transistor.

What is claimed is: 
     
         1 . An amplifier circuit for radio-frequency applications, comprising:
 an amplifying transistor having an input; and   a bias circuit including a first bias path implemented between a supply node and the input to provide a bias signal to the input of the amplifying transistor, and a second bias path implemented between the supply node and the input to provide an additional bias signal to the input of the amplifying transistor under a selected condition, the first bias path including a first transistor configured to facilitate the bias signal provided to the input of the amplifying transistor, the second bias path including a second transistor configured to facilitate the additional bias signal provided to the input of the amplifying transistor.   
     
     
         2 . The amplifier circuit of  claim 1  wherein the first bias path and the second bias path are implemented to be electrically parallel between the supply node and the input of the amplifying transistor. 
     
     
         3 . The amplifier circuit of  claim 1  wherein the amplifying transistor is a bipolar-junction transistor having a base as the input and a collector as an output. 
     
     
         4 . The amplifier circuit of  claim 3  wherein the first transistor of the first bias path is a field-effect transistor having a source, a drain, and a gate, the source coupled to the supply node, the drain coupled to the input of the amplifying transistor. 
     
     
         5 . The amplifier circuit of  claim 3  wherein the second transistor of the second bias path is a bipolar-junction transistor implemented in an emitter follower configuration with a collector coupled to the supply node and an emitter coupled to the input of the amplifying transistor. 
     
     
         6 . The amplifier circuit of  claim 5  wherein the emitter follower configuration further includes a base of the bipolar-junction transistor coupled to a node having a DC voltage. 
     
     
         7 . The amplifier circuit of  claim 6  wherein the emitter follower configuration is implemented so that an average emitter voltage of the bipolar-junction transistor increases with an increase in radio-frequency power at an input node of the amplifier circuit. 
     
     
         8 . The amplifier circuit of  claim 7  wherein the selected condition includes the increase in the radio-frequency power at the input node. 
     
     
         9 . The amplifier circuit of  claim 8  wherein the emitter follower configuration is further implemented so that the bipolar-junction transistor is in a conductive state when in the selected condition to thereby provide the additional bias signal to the input of the amplifying transistor. 
     
     
         10 . The amplifier circuit of  claim 9  wherein the additional bias signal provided to the input of the amplifying transistor is configured to reverse gain and phase droop associated with the amplifying transistor. 
     
     
         11 . The amplifier circuit of  claim 10  wherein the amplifying transistor is part of a driver stage. 
     
     
         12 . The amplifier circuit of  claim 11  further comprising a final stage, the DC voltage resulting in the additional bias signal is selected such that the reversal of gain and phase droop of the driver stage substantially coincides with a compression of the final stage. 
     
     
         13 . The amplifier circuit of  claim 12  wherein the DC voltage is selected such that the emitter follower configured bipolar-junction transistor is biased just below a turn-on level with a selected low radio-frequency power at the input node. 
     
     
         14 . The amplifier circuit of  claim 5  wherein the second bias path further includes a resistance between the emitter of the bipolar-junction transistor and the input of the amplifying transistor. 
     
     
         15 . The amplifier circuit of  claim 14  further comprising a capacitance that couples the emitter of the bipolar-junction transistor and the input node. 
     
     
         16 . The amplifier circuit of  claim 5  wherein the first bias path further includes a resistance between the drain of the field-effect transistor and the input of the amplifying transistor. 
     
     
         17 . The amplifier circuit of  claim 5  wherein the bias signal includes a bias current, and the additional bias signal includes an additional bias current. 
     
     
         18 . A packaged module for radio-frequency applications, comprising:
 a packaging substrate configured to receive a plurality of components; and   an amplifier circuit implemented on the packaging substrate and including an amplifying transistor having an input, the amplifier circuit further including a first bias path implemented between a supply node and the input to provide a bias signal to the input of the amplifying transistor, and a second bias path implemented between the supply node and the input to provide an additional bias signal to the input of the amplifying transistor under a selected condition, the first bias path including a first transistor configured to facilitate the bias signal provided to the input of the amplifying transistor, the second bias path including a second transistor configured to facilitate the additional bias signal provided to the input of the amplifying transistor.   
     
     
         19 . The packaged module of  claim 18  wherein the packaged module is a power amplifier module. 
     
     
         20 . A wireless device comprising:
 a transmit circuit configured to generate a signal;   an amplifier circuit configured to amplify the signal and including an amplifying transistor having an input, the amplifier circuit further including a first bias path implemented between a supply node and the input to provide a bias signal to the input of the amplifying transistor, and a second bias path implemented between the supply node and the input to provide an additional bias signal to the input of the amplifying transistor under a selected condition, the first bias path including a first transistor configured to facilitate the bias signal provided to the input of the amplifying transistor, the second bias path including a second transistor configured to facilitate the additional bias signal provided to the input of the amplifying transistor; and   an antenna in communication with the amplifier circuit and configured to facilitate transmission of the amplified signal.