US2017302279A1PendingUtilityA1

Semiconductor circuits

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Sep 1, 2015Filed: Jul 6, 2017Published: Oct 19, 2017
Est. expirySep 1, 2035(~9.1 yrs left)· nominal 20-yr term from priority
H03K 3/012H03K 19/0013H03K 3/037H03K 3/356121H03K 3/356104H03K 19/20H03K 3/356139H03K 19/018521H03K 19/0016H03K 19/017509
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Claims

Abstract

A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor circuit comprising:
 a first circuit configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and   a second circuit configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node, wherein
 when the voltage level of the clock signal is at a first level, the first node and the second node have different logical levels, 
 when the voltage level of the clock signal is at a second level, the first node and the second node have the same logical level, and 
 the second level is different from the first level.

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