Extended use of logarithm and exponent instructions

Abstract

Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.

What is claimed is: 
     
         1 . An apparatus for dividing a first input variable by a second input variable, the apparatus comprising:
 an absolute value circuit configured to compute an absolute value of the first input variable and an absolute value of the second input variable, and store a sign of the first input variable and a sign of the second input variable;   a logarithmic circuit configured to compute a logarithm of a first input value and a logarithm of a second input value, wherein the first input value is the absolute value of the first input variable and the second input value is the absolute value of the second input variable, and to provide the logarithm of the first input value and the logarithm of the second input value to a division circuit for subtracting the logarithm of the second input value from the logarithm of the first input value;   an exponential circuit configured to compute an exponent of a result of the subtracting by the division circuit; and   a sign decision circuit configured to generate a result of dividing the first input variable by the second input variable by combining the computed exponent with a sign indicative of a result of an XOR operation of the sign of the first input variable and the sign of the second input variable.   
     
     
         2 . The apparatus according to  claim 1 , wherein each of the first input value and the second input value is a floating point value. 
     
     
         3 . The apparatus according to  claim 1 , wherein each of the first input value and the second input value is a fixed point value. 
     
     
         4 . The apparatus according to  claim 1 , wherein the apparatus is implemented in an application specific integrated circuit (ASIC), a programmable gate array (PGA), or a digital signal processor (DSP). 
     
     
         5 . An apparatus for multiplying a first input variable and a second input variable, the apparatus comprising:
 an absolute value circuit configured to compute an absolute value of the first input variable and an absolute value of the second input variable, and store a sign of the first input variable and a sign of the second input variable;   a logarithmic circuit configured to compute a logarithm of a first input value and a logarithm of a second input value, wherein the first input value is the absolute value of the first input variable and the second input value is the absolute value of the second input variable, and to provide the logarithm of the first input value and the logarithm of the second input value to a multiplication circuit for adding the logarithm of the first input value and the logarithm of the second input value;   an exponential circuit configured to compute an exponent of a result of the adding by the multiplication circuit; and   a sign decision circuit configured to generate a result of multiplying the first input variable and the second input variable by combining the computed exponent with a sign indicative of a result of an XOR operation of the sign of the first input variable and the sign of the second input variable.   
     
     
         6 . The apparatus according to  claim 5 , wherein each of the first input value and the second input value is a floating point value. 
     
     
         7 . The apparatus according to  claim 5 , wherein each of the first input value and the second input value is a fixed point value. 
     
     
         8 . The apparatus according to  claim 5 , wherein the apparatus is implemented in an application specific integrated circuit (ASIC), a programmable gate array (PGA), or a digital signal processor (DSP). 
     
     
         9 . A method for computing a function of a first input variable and a second input variable, the method comprising:
 using an absolute value circuit to compute an absolute value of the first input variable and an absolute value of the second input variable, and store a sign of the first input variable and a sign of the second input variable;   using a logarithmic circuit configured to compute a logarithm of a first input value and a logarithm of a second input value, wherein the first input value is the absolute value of the first input variable and the second input value is the absolute value of the second input variable, and to provide the logarithm of the first input value and the logarithm of the second input value to a further circuit for generating an intermediate logarithmic result by subtracting the logarithm of the second input value from the logarithm of the first input value if the function is division, and/or   adding the logarithm of the first input value and the logarithm of the second input value if the function is multiplication;   an exponential circuit configured to compute an exponent of the intermediate logarithmic result; and   a sign decision circuit configured to generate a result of the function by combining the computed exponent with a sign that is a result of an XOR operation of the sign of the first input variable and the sign of the second input variable.   
     
     
         10 . The method according to  claim 9 , wherein each of the first input value and the second input value is a floating point value. 
     
     
         11 . The method according to  claim 9 , wherein each of the first input value and the second input value is a fixed point value.