US2017317107A1PendingUtilityA1

Novel silicon-based backplane structures and methods for display applications

Assignee: KUMAR ANANDA HPriority: Nov 5, 2013Filed: Jul 3, 2017Published: Nov 2, 2017
Est. expiryNov 5, 2033(~7.3 yrs left)· nominal 20-yr term from priority
H10W 10/181H10P 90/1916H01L 2227/323H01L 27/3244H01L 27/1229H01L 21/76254H01L 51/56H01L 27/127H10D 86/471H10D 86/425H10D 86/60H10D 86/0221H10K 59/1201
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Displays can be fabricated using driver transistors formed with high quality semiconductor channel materials, and switching transistors formed with low quality semiconductor channel materials. The driver transistors can require high forward current to drive emission of the OLED pixels, but might not require very low leakage current. The switching transistors can require low leakage current to allow the pixel capacitor to retain the signal level for accurate OLED device emission, preventing abnormal displays or cross talks.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A display comprising
 a transparent substrate, wherein the transparent substrate comprises a layer of single crystal silicon on a portion of the transparent substrate;   a first device, wherein the first device is formed on the single crystal silicon layer, wherein the first device is configured to use the single crystal silicon layer as a first device channel;   a second device, wherein the second device is formed on the transparent substrate, wherein the second device is configured to use an amorphous or polycrystalline silicon layer as a second device channel;   a pixel on the transparent substrate, wherein the pixel is configured to be driven by the first device, wherein the pixel is configured to be switched by the second device.   
     
     
         2 . A display as in  claim 1   wherein the transparent substrate comprises a glass substrate.   
     
     
         3 . A display as in  claim 1   wherein the layer of single crystal silicon comprises a thickness between 0.2 and 5 microns.   
     
     
         4 . A display as in  claim 1   wherein the layer of amorphous silicon comprises a thickness between 100 and 1000 nm.   
     
     
         5 . A display as in  claim 1   wherein the layer of single crystal silicon is bonded to the transparent substrate by stiction.   
     
     
         6 . A display as in  claim 1   wherein the layer of single crystal silicon comprises an oxide layer facing the transparent substrate.   
     
     
         7 . A display as in  claim 1   wherein the first device comprises a single crystal silicon gate, together with a source and a drain.   
     
     
         8 . A method as in  claim 1   wherein the first device is configured to supply a power to the pixel,   
     
     
         9 . A method as in  claim 1   wherein the second device is formed directly on the transparent substrate.   
     
     
         10 . A display as in  claim 1   wherein the second device comprises an amorphous silicon gate, together with a source and a drain.   
     
     
         11 . A method as in  claim 1   wherein the second device is configured to control the power supplied to the pixel.   
     
     
         12 . A display as in  claim 1  further comprising
 electrical connections connecting the first device, the second device, and the pixel. 
 
     
     
         13 . A display as in  claim 1   wherein the pixel comprises an organic light emitting diode (OLED) pixel.   
     
     
         14 . A display as in  claim 1   wherein the first device is configured to supply a current to the pixel,   wherein the second device is configured to control the current supplied to the pixel.   
     
     
         15 . A display comprising
 a transparent substrate;   a first device, wherein the first device is formed on the transparent substrate, wherein the first device is configured to use the single crystal silicon layer as a first device channel, wherein the first device is configured to drive a display pixel;   a second device, wherein the second device is formed on the transparent substrate, wherein the second device is configured to use an amorphous or polycrystalline silicon layer as a second device channel, wherein the second device is configured to switch the display pixel.   
     
     
         16 . A display as in  claim 15   wherein the first device is formed on a single crystal silicon layer on the transparent substrate.   
     
     
         17 . A display as in  claim 15   wherein the pixel comprises an organic light emitting diode (OLED) pixel,   wherein the first device is configured to supply a current to the pixel,   wherein the second device is configured to control the current supplied to the pixel.   
     
     
         18 . A display comprising
 a transparent substrate comprising a single crystal silicon device and an amorphous or polycrystalline silicon device,   wherein the single crystal silicon device is configured to drive a display pixel,   wherein the amorphous or polycrystalline silicon device is configured to switch the display pixel.   
     
     
         19 . A display as in  claim 18   wherein the single crystal silicon device is formed on a single crystal silicon layer on the transparent substrate.   
     
     
         20 . A display as in  claim 18   wherein the pixel comprises an organic light emitting diode (OLED) pixel,   wherein the single crystal silicon device is configured to supply a current to the pixel,   wherein the amorphous or polycrystalline silicon device is configured to control the current supplied to the pixel.

Join the waitlist — get patent alerts

Track US2017317107A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.