Nonvolatile bipolar junction memory cell

Abstract

The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a conductive anodic filament extending from the collector layer to the base layer. As current is applied to the transistor and a voltage is applied between P-N junction of the collector layer and the base layer, a conductive anodic filament (CAF) forms. The CAF is non-volatile and short circuits the reverse-biased P-N junction barrier thus keeping the device in a low-resistive state. Removing the CAF switches the device back to a high resistive state. Thus, a new type of semiconductor device advantageously combines computation and memory to form a flux-linkage modulated memory cell.

What is claimed is: 
     
         1 . A bipolar junction memory device, comprising:
 a collector layer comprised of copper oxide;   a base layer comprised of copper-indium oxide disposed on the collector layer;   an emitter layer comprised of copper oxide disposed on the base layer;   an insulating layer disposed on the collector layer, the base layer, and the emitter layer;   a first metalized contact disposed on the insulating layer in contact with the emitter layer;   a second metalized contact disposed on the insulating layer in contact with the base layer; and   a third metalized contact disposed on the insulating layer in contact with the collector layer.   
     
     
         2 . The device of  claim 1 , wherein the collector layer is N-conducting. 
     
     
         3 . The device of  claim 2 , wherein the base layer is P-conducting. 
     
     
         4 . The device of  claim 3 , wherein the emitter layer is N-conducting. 
     
     
         5 . The device of  claim 1 , wherein the metalized contact is a conductive metal selected from the group consisting of copper (Cu) or tungsten (W). 
     
     
         6 . The device of  claim 1 , wherein the collector layer is P-conducting, the base layer is N-conducting, and the emitter layer is P-conducting. 
     
     
         7 . A bipolar memory junction device, comprising:
 a collector layer;   a base layer disposed on the collector layer;   an emitter layer disposed on the base layer;   a first PN junction formed at the interface of the base layer and the emitter layer; and   a second PN junction formed at the interface of the base layer and the collector layer, wherein the second PN junction can be reversibly short-circuited.   
     
     
         8 . The device of  claim 7 , wherein the collector layer is N-conducting. 
     
     
         9 . The device of  claim 8 , wherein the base layer is P-conducting. 
     
     
         10 . The device of  claim 9 , wherein the emitter layer is N-conducting. 
     
     
         11 . The device of  claim 7 , wherein the collector layer is P-conducting. 
     
     
         12 . The device of  claim 11 , wherein the base layer is N-conducting. 
     
     
         13 . The device of  claim 12 , wherein the emitter layer is P-conducting. 
     
     
         14 . The device of  claim 7 , wherein the base layer, collector layer and emitter layer each comprise compounds that include copper.