Performing Rounding Operations Responsive To An Instruction

Abstract

In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a source vector register to store a plurality of packed double-precision floating-point values associated with a source operand of a round instruction; and   an execution circuit to round the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, the execution circuit to round in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode to be used by the execution circuit and a second set of one or more bits to indicate whether a precision exception is to be suppressed.   
     
     
         2 . The processor of  claim 1  further comprising:
 circuitry to decode the immediate to determine the rounding mode to be used by the execution circuit and to determine whether the precision exception is to be suppressed. 
 
     
     
         3 . The processor of  claim 1  wherein in response to the first set of one or more bits having a first value, the execution circuit is to select a nearest rounding mode to generate a rounded result corresponding to a nearest integer value. 
     
     
         4 . The processor of  claim 3  wherein in response to the first set of one or more bits having a second value, the execution circuit is to select a truncate rounding mode to generate a truncated result. 
     
     
         5 . The processor of  claim 4  wherein in response to the first set of one or more bits having a third value or a fourth value, the execution circuit is to select a rounding mode towards negative infinity or a rounding mode towards positive infinity, respectively. 
     
     
         6 . The processor of  claim 1  wherein the execution circuit is a floating point execution circuit. 
     
     
         7 . The processor of  claim 1  further comprising:
 a plurality of cores, the execution circuit integral to one of the plurality of cores. 
 
     
     
         8 . The processor of  claim 1  further comprising:
 a communication interconnect to couple the processor to one or more devices. 
 
     
     
         9 . The processor of  claim 8  wherein the communication interconnect comprises a Peripheral Component Interconnect Express (PCIe) interconnect. 
     
     
         10 . A method comprising:
 storing a plurality of packed double-precision floating-point values associated with a source operand of a round instruction in a source vector register; and   rounding the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, wherein rounding is perform in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode and a second set of one or more bits to indicate whether a precision exception is to be suppressed.   
     
     
         11 . The method of  claim 10  further comprising:
 decoding the immediate to determine the rounding mode to be used and to determine whether the precision exception is to be suppressed. 
 
     
     
         12 . The method of  claim 10  wherein in response to the first set of one or more bits having a first value, selecting a nearest rounding mode to generate a rounded result corresponding to a nearest integer value. 
     
     
         13 . The method of  claim 12  wherein in response to the first set of one or more bits having a second value, selecting a truncate rounding mode to generate a truncated result. 
     
     
         14 . The method of  claim 13  wherein in response to the first set of one or more bits having a third value or a fourth value, selecting a rounding mode towards negative infinity or a rounding mode towards positive infinity, respectively. 
     
     
         15 . A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
 storing a plurality of packed double-precision floating-point values associated with a source operand of a round instruction in a source vector register; and   rounding the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, wherein rounding is perform in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode and a second set of one or more bits to indicate whether a precision exception is to be suppressed.   
     
     
         16 . The machine-readable medium of  claim 15  further comprising program code to cause the machine to perform the operation of:
 decoding the immediate to determine the rounding mode to be used and to determine whether the precision exception is to be suppressed. 
 
     
     
         17 . The machine-readable medium of  claim 15  further comprising program code to cause the machine to perform the operation of:
 in response to the first set of one or more bits having a first value, selecting a nearest rounding mode to generate a rounded result corresponding to a nearest integer value. 
 
     
     
         18 . The machine-readable medium of  claim 17  further comprising program code to cause the machine to perform the operation of:
 in response to the first set of one or more bits having a second value, selecting a truncate rounding mode to generate a truncated result. 
 
     
     
         19 . The machine-readable medium of  claim 18  further comprising program code to cause the machine to perform the operation of
 in response to the first set of one or more bits having a third value or a fourth value, selecting a rounding mode towards negative infinity or a rounding mode towards positive infinity, respectively.