Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits

Abstract

One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slew max within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.

1 . A computer-implemented method of synthesizing a multi-corner mesh-based clock distribution network for a multi-voltage domain in an integrated circuit, the method comprising:
 (a) for each of a plurality of voltage domains, placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slew max  within the voltage domain i exceeds a defined slew threshold;   (b) calculating maximum insertion delay values for all cases for each of the voltage domains;   (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j:
 (i) adding a max size buffer to all voltage domains except voltage domain j; and 
 (ii) repeating steps (b) and (c); 
   (d) reducing buffer sizes for each of the voltage domains, in order of decreasing skew, by:
 (i) downsizing all buffers in a k-th level of the voltage domain; 
 (ii) if the downsizing step (i) does not improve a calculated skew across the plurality of voltage domains, (1) undoing the downsizing step (d)(i) and (2) performing substep (i) for the k+1th level of the voltage domain; and 
 (iii) otherwise, repeating substep (d)(i); 
   (e) recalculating maximum insertion delay values for all cases for each of the voltage domains; and   (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.   
     
     
         2 . The computer-implemented method of  claim 1 , wherein “all cases” include a best case, a nominal case, and a worst case. 
     
     
         3 . The computer-implemented method of  claim 1 , wherein the calculated skew is the largest difference between a maximum insertion delay and a minimum insertion delay within one of the voltage domains. 
     
     
         4 . A tangible, non-transitory computer-readable medium comprising computer-program instructions for implementing an electronics design automation program implementing a method of synthesizing a multi-corner mesh-based clock distribution network for a multi-voltage domain in an integrated circuit, the method comprising:
 (a) for each of a plurality of voltage domains, placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slew max  within the voltage domain i exceeds a defined slew threshold;   (b) calculating maximum insertion delay values for all cases for each of the voltage domains;   (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j:
 (i) adding a max size buffer to all voltage domains except voltage domain j; and 
 (ii) repeating steps (b) and (c); 
   (d) reducing buffer sizes for each of the voltage domains, in order of decreasing skew, by:
 (i) downsizing all buffers in a k-th level of the voltage domain; 
 (ii) if the downsizing step (i) does not improve a calculated skew across the plurality of voltage domains, (1) undoing the downsizing step (d)(i) and (2) performing substep (i) for the k+1th level of the voltage domain; and 
 (iii) otherwise, repeating substep (d)(i); 
   (e) recalculating maximum insertion delay values for all cases for each of the voltage domains; and   (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.   
     
     
         5 . The tangible, non-transitory computer-readable medium of  claim 4 , wherein “all cases” include a best case, a nominal case, and a worst case. 
     
     
         6 . The tangible, non-transitory computer-readable medium of  claim 4 , wherein the calculated skew is the largest difference between a maximum insertion delay and a minimum insertion delay within one of the voltage domains. 
     
     
         7 . An integrated circuit comprising:
 a clock mesh topology having multiple voltage islands sharing a single clock domain.   
     
     
         8 . The integrated circuit of  claim 7 , wherein the maximum insertion delay path is placed in the highest voltage domain