Physical Layer for Peripheral Interconnect with Reduced Power and Area

Abstract

An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

What is claimed is: 
     
         1 . An integrated circuit having a peripheral interconnect to communicate with a peripheral device according to an industry standard specification that specifies a link having a transmit portion and a receive portion, the integrated circuit comprising:
 a physical interface layer circuit, wherein the physical interface layer circuit is configured to:
 drive N lanes on the transmit portion; and 
 receive M lanes on the receive portion, wherein N and M are positive integers and are not equal. 
   
     
     
         2 . The integrated circuit as recited in  claim 1  wherein a first bandwidth on the transmit portion is greater than a second bandwidth on the receive portion during use, and wherein N is greater than M. 
     
     
         3 . The integrated circuit as recited in  claim 1  wherein a first bandwidth on the transmit portion is less than a second bandwidth on the receive portion during use, and wherein N is less than M. 
     
     
         4 . The integrated circuit as recited in  claim 1  wherein the industry standard specification specifies symmetric transmit and receive portions. 
     
     
         5 . The integrated circuit as recited in  claim 4  further comprising a controller circuit configured to provide a media access control layer interface to the peripheral interconnect that complies with the industry standard specification, wherein the controller circuit is coupled to the physical interface layer circuit. 
     
     
         6 . The integrated circuit as recited in  claim 1  wherein the transmit portion and the receive portion are single-ended. 
     
     
         7 . The integrated circuit as recited in  claim 1  wherein the M lanes are unterminated. 
     
     
         8 . The integrated circuit as recited in  claim 1  wherein the N lanes and the M lanes are unidirectional, point-to-point lanes. 
     
     
         9 . A system comprising:
 an integrated circuit; and   a peripheral coupled to the integrated circuit using an interconnect having a transmit side on which the integrated circuit is configured to transmit packets to the peripheral and a receive side on which the peripheral is configured to transmit packets to the integrated circuit, wherein the interconnect is asymmetric.   
     
     
         10 . The system as recited in  claim 9  wherein an amount of asymmetry is determined based on relative amounts of bandwidth expected on the transmit side and the receive side. 
     
     
         11 . The system as recited in  claim 9  wherein the transmit side comprises N lanes and the receive side comprises M lanes, wherein M and N are positive integers and are not equal. 
     
     
         12 . The system as recited in  claim 11  wherein the N lanes and the M lanes are unidirectional, point-to-point connections. 
     
     
         13 . The system as recited in  claim 11  wherein a first bandwidth on the transmit side is expected to be greater than a second bandwidth on the receive side during use, and wherein N is greater than M. 
     
     
         14 . The system as recited in  claim 11  wherein a first bandwidth on the transmit side is expected to be less than a second bandwidth on the receive side during use, and wherein N is less than M. 
     
     
         15 . The system as recited in  claim 11  wherein the N lanes and the M lanes are unterminated at an end at which the packets are received. 
     
     
         16 . The system as recited in  claim 11  wherein the N lanes and the M lanes implement single-ended signalling. 
     
     
         17 . An integrated circuit having a peripheral interconnect to communicate with a peripheral device according to an industry standard specification that specifies a link have a transmit portion and a receive portion, the integrated circuit comprising:
 a controller circuit configured to provide a media access control layer interface to the peripheral interconnect that complies with the industry standard specification; and   a physical interface layer circuit coupled to the controller circuit, wherein the physical interface layer circuit is configured to:
 drive packets from the controller circuit on the transmit portion; and 
 receive packets on the receive portion and forward the packets to the controller circuit, wherein the receive portion and the transmit portion are asymmetric. 
   
     
     
         18 . The integrated circuit as recited in  claim 17  wherein an amount of asymmetry is determined based on relative amounts of bandwidth expected on the transmit portion and the receive portion. 
     
     
         19 . The integrated circuit as recited in  claim 17  wherein the transmit portion comprises N lanes and the receive portion comprises M lanes, wherein M and N are positive integers and are not equal. 
     
     
         20 . The integrated circuit as recited in  claim 19  wherein the N lanes and the M lanes are unidirectional, point-to-point connections.