System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips

Abstract

Methods, apparatus, and systems, for interfacing one or more storage devices with a plurality of bridge chips. An apparatus may include a memory, a communication bus coupled to a device, and a processor communicatively coupled to the communication bus and the memory. The processor may be configured to implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips. The processor may be further configured to multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.

What is claimed is: 
     
         1 . An apparatus comprising:
 a memory;   a communication bus coupled to a device; and   a processor communicatively coupled to the communication bus and the memory, the processor configured to
 implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips, the first bridge chip comprising a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group, 
 multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and 
 distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the first bridge chip is configurable to assume a first configuration such that information from the storage device presented to the first port group is sent to a selected one of the second port group and the third port group and is further configurable to assume a second configuration such that information from the storage device presented to the first port group is sent to the second port group and the third port group. 
     
     
         3 . The apparatus of  claim 1 , wherein the processor is further configured to, responsive to a condition in which all resources of one of the plurality of bridge chips are in use, distribute data across other bridge chips of the plurality of bridge chips. 
     
     
         4 . The apparatus of  claim 1 , wherein the first port group is a mass-storage-side port group, and the second port group and the third port group are mass-storage-utilizing-side port groups. 
     
     
         5 . The apparatus of  claim 1 , wherein performance of the multiplexing of the storage traffic is based upon a combination of protocol translation resources of the plurality of bridge chips. 
     
     
         6 . The apparatus of  claim 1 , wherein the storage device is compatible with a first storage protocol and the central processor is compatible with a second storage protocol, and wherein the processor is further configured to provide interoperation between the storage device and the central processor. 
     
     
         7 . The apparatus of  claim 1 , wherein a performance of a selected one of the multiplexing of first storage traffic and the multiplexing of second storage traffic is based upon a combination of protocol translation resources of the plurality of bridge chips. 
     
     
         8 . The apparatus of  claim 1 , wherein each of the bridge chips communicates with each other via a plurality of communication links, and wherein at least one communication link of the plurality of communication links is configured such that each of the plurality of bridge chips is capable of communicating with each other of the plurality of bridge chips. 
     
     
         9 . The apparatus of  claim 1 , wherein at least one communication link of the plurality of communication links is configured to be utilized for error recovery. 
     
     
         10 . The apparatus of  claim 1 , wherein at least one communication link of the plurality of communication links is configured to be utilized for vendor unique communication. 
     
     
         11 . The apparatus of  claim 1 , wherein at least one of the plurality of groups of ports of the at least one of the plurality of bridge chips configured to multiplex storage traffic comprises a plurality of input ports. 
     
     
         12 . A method, comprising;
 implementing storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips, the first bridge chip comprising a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group;   multiplexing, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips; and   distributing data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.   
     
     
         13 . The method of  claim 12 , wherein the first bridge chip is configurable to assume a first configuration such that information from the storage device presented to the first port group is sent to a selected one of the second port group and the third port group and is further configurable to assume a second configuration such that information from the storage device presented to the first port group is sent to the second port group and the third port group. 
     
     
         14 . The method of  claim 12 , further comprising distributing data across other bridge chips of the plurality of bridge chips responsive to a condition in which all resources of a particular one of the plurality of bridge chips are in use. 
     
     
         15 . The method of  claim 12 , wherein the first port group is a mass-storage-side port group, and the second port group and the third port group are mass-storage-utilizing-side port groups. 
     
     
         16 . The method of  claim 12 , wherein performance of the multiplexing of the storage traffic is based upon a combination of protocol translation resources of the plurality of bridge chips. 
     
     
         17 . A system comprising:
 a storage device;   a multiplexing bridge chip configured to multiplex data and to distribute data, the multiplexing bridge chip comprising a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group, the first port group being a mass-storage-side port group, the second port group and the third port group being mass-storage-utilizing-side port groups;   a first bridge chip and a second bridge chip connected to the multiplexing bridge chip, the first bridge chip and the second bridge chip each configured to distribute data,   a first output port associated with the first bridge chip;   a second output port associated with the second bridge chip; and   a communication link connecting the storage device to the multiplexing bridge chip and allowing information from the storage device presented to the first port group to be sent to a selected one of the second port group and the third port group.   
     
     
         18 . The system of  claim 17 , wherein the communication link is a first communication link, and wherein the first bridge chip and the second bridge chip are connected by a second communication link. 
     
     
         19 . The system of  claim 18 , wherein the multiplexing bridge chip is a first multiplexing bridge chip, the first multiplexing bridge chip is connected to a second multiplexing bridge chip by a third communication link, the second multiplexing bridge chip is configured to multiplex data and to perform protocol translations, and the first and second multiplexing bridge chip are connected to a multiplexer to perform additional multiplexing functionality. 
     
     
         20 . The system of  claim 17 , wherein performance of the multiplexing of storage traffic is based upon a combination of protocol translation resources of the plurality of bridge chips.