Finfet and manufacturing method of the same

Abstract

A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.

What is claimed is: 
     
         1 . A fin field effect transistor (FinFET) comprising:
 a semiconductor substrate comprising a plurality of insulating areas;   a fin structure disposed to extend on the semiconductor substrate between two of the insulating areas;   a gate dielectric layer disposed to extend across two sides of the fin structure;   a gate electrode structure disposed on the gate dielectric layer;   a drain structure disposed at a first side of the fin structure relative to the gate electrode structure and has a first resistance relative to the gate electrode; and   a source structure disposed at a second side of the fin structure relative to the gate electrode structure and has a second resistance relative to the gate electrode, wherein the first resistance is larger than the second resistance.   
     
     
         2 . The FinFET of  claim 1 , wherein the drain structure and the gate electrode structure have a first distance therebetween, and the source structure and the gate electrode structure have a second distance therebetween, wherein the first distance is larger than the second distance. 
     
     
         3 . The FinFET of  claim 1 , further comprising a plurality of the fin structures, a plurality of the drain structures and a plurality of the source structures, wherein the plurality of the drain structures correspond to the fin structures and the plurality of the drain structures are electrically coupled to each other, the plurality of the source structures correspond to the fin structures and the plurality of the source structures are electrically coupled to each other. 
     
     
         4 . The FinFET of  claim 1 , wherein the fin structure further comprises a trench between the gate electrode structure and the drain structure. 
     
     
         5 . The FinFET of  claim 4 , wherein a depth of the trench is smaller than or equal to the height of the fin structure relative to the semiconductor substrate. 
     
     
         6 . A FinFET manufacturing method comprising:
 providing a transistor precursor that comprises:
 a semiconductor substrate comprising a plurality of insulating areas; 
 a fin structure disposed to extend on the semiconductor substrate between two of the insulating areas; 
 a gate dielectric layer disposed to extend across two sides of the fin structure; and 
 a gate electrode structure disposed on the gate dielectric layer; 
   performing etching on a first position and a second position of the fin structure, wherein the first position is at a first side of the fin structure relative to the gate electrode structure and the second position is at a second side of the fin structure relative to the gate electrode structure; and   forming a drain structure at the first position and forming a source structure at the second position, wherein the drain structure has a first resistance relative to the gate electrode and the source structure has a second resistance relative to the gate electrode, and the first resistance is larger than the second resistance.   
     
     
         7 . The FinFET manufacturing method of  claim 6 , further comprising:
 forming the drain structure such that the drain structure and the gate electrode structure have a first distance therebetween and forming the source structure such that the source structure and the gate electrode structure have a second distance therebetween, wherein the first distance is larger than the second distance.   
     
     
         8 . The FinFET manufacturing method of  claim 6 , wherein the transistor precursor further comprises a plurality of fin structures, and the FinFET manufacturing method further comprises:
 performing etching on a first position and a second position of each of the plurality of fin structures, wherein the first position is at a first side of the gate electrode structure and the second position is at a second side of the gate electrode structure; and   forming a plurality of drain structures each at the first position of each of the plurality of fin structures and forming a plurality of source structures each at the second position of each of the plurality of fin structures; and   electrically coupling the plurality of drain structures and electrically coupling the plurality of source structures.   
     
     
         9 . The FinFET manufacturing method of  claim 6 , further comprising:
 forming a trench between the gate electrode structure and the first position of the fin structure.   
     
     
         10 . The FinFET manufacturing method of  claim 9 , wherein a depth of the trench is smaller than or equal to the height of the fin structure relative to the semiconductor substrate.