Monitoring packet residence time and correlating packet residence time to input sources

Abstract

An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.

1 - 20 . (canceled) 
     
     
         21 . A device, comprising:
 one or more processors to:
 compute, based on counter information associated with an output queue, an average residence time associated with the output queue,
 the average residence time corresponding to an amount of time that a group of packets are located in the output queue; 
 
 determine, based on computing the average residence time, whether a latency event associated with the output queue has occurred; 
 determine, based on determining that the latency event has occurred, input queue performance information associated with an input queue corresponding to the output queue; and 
 provide input queue performance information associated with the input queue. 
   
     
     
         22 . The device of  claim 21 , where the one or more processors are further to:
 receive an indication to determine whether a latency event has occurred; and   determine the counter information based on receiving the indication.   
     
     
         23 . The device of  claim 21 , where the device is configured to automatically determine whether a latency event associated with the output queue has occurred at a particular time interval. 
     
     
         24 . The device of  claim 21 , where the one or more processors are further to:
 determine the counter information for a most recent interval of time.   
     
     
         25 . The device of  claim 21 , where the one or more processors are further to:
 determine the counter information based on information stored by an output packet processing chip.   
     
     
         26 . The device of  claim 21 , where the one or more processors, when computing the average residence time, are to:
 compute the average residence time based on a quantity of the group of packets and a total residence time of the group of packets.   
     
     
         27 . The device of  claim 21 , where the latency event includes an event indicating that the output queue has experienced an amount of latency that exceeds a threshold amount. 
     
     
         28 . A method, comprising:
 computing, by the device and based on counter information associated with an output queue, an average residence time associated with the output queue,
 the average residence time corresponding to an amount of time that a group of packets are located in the output queue; 
   determining, by the device and based on computing the average residence time, whether a latency event associated with the output queue has occurred;   determining, by the device and based on determining that the latency event has occurred, input queue performance information associated with an input queue corresponding to the output queue; and   providing, by the device, input queue performance information associated with the input queue.   
     
     
         29 . The method of  claim 28 , further comprising:
 comparing the average residence time and an average residence time threshold; and   where determining whether the latency event has occurred comprises:
 determining whether the latency event has occurred based on comparing the average residence time to the average residence time threshold. 
   
     
     
         30 . The method of  claim 28 , further comprising:
 determining a maximum residence time of any packet provided by the output queue during an interval of time; and   comparing the maximum residence time and a maximum residence time threshold; and   where determining whether the latency event has occurred comprises:
 determining whether the latency event has occurred based on comparing the maximum residence time and the maximum residence time threshold. 
   
     
     
         31 . The method of  claim 28 , further comprising:
 providing the counter information based on determining that the latency event has occurred.   
     
     
         32 . The method of  claim 28 , where the latency event is a first latency event;
 where the counter information is first counter information; and   where the method further comprises:
 determining that a second latency event has not occurred,
 second counter information not being provided based on determining that the second latency even has not occurred. 
 
   
     
     
         33 . The method of  claim 28 , where the latency event is a first latency event;
 where the counter information is first counter information; and   where the method further comprises:
 determining that a second latency event has not occurred; and 
 determining second counter information at a subsequent time interval. 
   
     
     
         34 . The method of  claim 28 , further comprising:
 providing a latency event notification comprising:
 information that identifies the latency event, and 
 information identifying a time of day associated with the latency event. 
   
     
     
         35 . A non-transitory computer-readable medium storing instructions, the instructions comprising:
 one or more instructions that, when executed by one or more processors, cause the one or more processors to:
 compute, based on counter information associated with an output queue, an average residence time associated with the output queue,
 the average residence time corresponding to an amount of time that a group of packets are located in the output queue; 
 
 determine, based on computing the average residence time, whether a latency event associated with the output queue has occurred; and 
 provide, based on determining that the latency event has occurred, input queue performance information associated with an input queue. 
   
     
     
         36 . The non-transitory computer-readable medium of  claim 35 , where the one or more instructions, when executed by the one or more processors, further cause the one or more processors to:
 provide a latency event notification to an input packet processing chip managing the input queue.   
     
     
         37 . The non-transitory computer-readable medium of  claim 36 , where the one or more instructions, when executed by the one or more processors, further cause the one or more processors to:
 identify the input queue based on the latency event notification.   
     
     
         38 . The non-transitory computer-readable medium of  claim 36 , where the one or more instructions, when executed by the one or more processors, further cause the one or more processors to:
 monitor the input queue for a period of time based on the latency event notification.   
     
     
         39 . The non-transitory computer-readable medium of  claim 35 , where the one or more instructions, when executed by the one or more processors, further cause the one or more processors to:
 determine congestion information for the input queue,
 the congestion information including information regarding at least one of:
 packet loss rate, or 
 queue depth. 
 
   
     
     
         40 . The non-transitory computer-readable medium of  claim 39 , where the congestion information includes information regarding a class of packets.