Increasing manufacturing yield of integrated circuits by modifying original design layout using location specific constraints

Abstract

An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

1 . An integrated circuit (IC) product manufactured using an IC fabrication system by a process comprising, steps of:
 providing an original design layout;   providing original global limits on relative distance between layout objects;   detecting at least one critical area in the original design layout that includes at least one pattern that increases manufacturing defect risk;   generating at least one location specific modification to the original global limits on relative distance between layout objects, the location specific modifications comprising a first location specific limit on relative distance between layout objects for the at least one critical area is the original design layout, wherein the first location specific limit reduces manufacturing defect risk for the first area;   modifying the original design layout by enforcing the original global limits on relative distance between layout objects with the location specific modifications to generate a modified design layout, the modified design layout being different from the original design layout, so that the original design rules and the location specific constraints work together to improve chip yield;   storing the modified design layout to a memory device;   wherein the steps of detecting, generating, and modifying are performed by a processing system comprising a memory device storing application software, a user interface, and a processor coupled to the memory device and to the user interface.   
     
     
         2 . The integrated circuit product of  claim 1 , wherein a dimension of a plurality of first directionally oriented layout objects of a first type of the modified design layout is substantially different from same dimension of second directionally oriented layout objects of the first type, the first directionally oriented layout objects being oriented along a first direction, the second directionally oriented layout objects being oriented along a second direction, the second direction being orthogonal to the first direction. 
     
     
         3 . The integrated circuit product of  claim 2 , wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects reside in the same layer of the modified design layout. 
     
     
         4 . The integrated circuit product of  claim 3 , wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects are conductors. 
     
     
         5 . The integrated circuit product of  claim 1 , wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values. 
     
     
         6 . The integrated circuit product of  claim 5 , wherein the first plurality of routing wires and the second plurality of routing wires reside in the same layer of the modified design layout. 
     
     
         7 . The integrated circuit product of  claim 1 , wherein the original design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances. 
     
     
         8 . The integrated circuit product of  claim 1 , wherein the first area includes interrelated layout objects on one layer. 
     
     
         9 . The integrated circuit product of  claim 8 , wherein the step of generating the location specific constraints comprises comparing known geometry combinations. 
     
     
         10 . The integrated circuit product of  claim 9 , wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table. 
     
     
         11 . The integrated circuit product of  claim 8 , wherein the step of generating the location specific constraints comprises performing pattern recognition. 
     
     
         12 . The integrated circuit product of  claim 8 , wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one interrelated layout object. 
     
     
         13 . The integrated circuit product of  claim 8 , wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent interrelated layout objects. 
     
     
         14 . The integrated circuit product of  claim 13 , wherein the at least two adjacent interrelated layout objects are conductors. 
     
     
         15 . The integrated circuit product of  claim 1 , wherein the step of generating the location specific constraints comprises comparing known geometry combinations. 
     
     
         16 . The integrated circuit product of  claim 15 , wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table. 
     
     
         17 . The integrated circuit product of  claim 1 , wherein the step of generating the location specific constraints comprises performing pattern recognition. 
     
     
         18 . The integrated circuit product of  claim 1 , wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one layout object. 
     
     
         19 . The integrated circuit product of  claim 1 , wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent layout objects. 
     
     
         20 . The integrated circuit product of  claim 1 , wherein:
 the original global design rules comprise a first minimum safeguard distance constraint; and   the step of generating the location specific constraints comprises generating a first additional safeguard distance, and adding the first additional safeguard distance to the first minimum distance to obtain the first location specific constraint.   
     
     
         21 . The integrated circuit product of  claim 1 , wherein application of the original global design rules together with the first location specific constraint in the first area is more restrictive than application of the original global design rules without application of the first location specific constraint in the first area, whereby the modified design layout satisfies the original global design riles. 
     
     
         22 . A method of improving manufacturing yield for an integrated circuit by a processing system comprising a memory device storing application software, a user interface, and a processor coupled to the memory device and to the user interface comprising the steps of:
 providing an original design layout;   providing original global limits on relative distance between layout objects;   detecting at least one critical area in the original design layout that includes at least one pattern that increases manufacturing defect risk;   generating at least one location specific modification to the original global limits on relative distance between layout objects, the location specific modifications comprising a first location specific limit on relative distance between layout objects for the at least one critical area in the original design layout, wherein the first location specific limit reduces manufacturing defect risk for the first area;   modifying the original design layout by enforcing the original global limits on relative distance between layout objects with the location specific modifications to generate a modified design layout, the modified design layout being different from the original design layout, so that the original design rules and the location specific constraints work together to improve chip yield;   storing the modified design layout to a memory device.   
     
     
         23 . The method of  claim 22 , wherein a dimension of a plurality of first directionally oriented layout objects of a first type of the modified design layout is substantially different from same dimension of second directionally oriented layout objects of the first type, the first directionally oriented layout objects being oriented along a first direction, the second directionally oriented layout objects being oriented along a second direction, the second direction being orthogonal to the first direction. 
     
     
         24 . The method of  claim 23 , wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects reside in the same layer of the modified design layout. 
     
     
         25 . The method of  claim 24 , wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects are conductors. 
     
     
         26 . The method of  claim 22 , wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values. 
     
     
         27 . The method of  claim 22 , wherein the first plurality of routing wires and the second plurality of routing wires reside in the same layer of the modified design layout. 
     
     
         28 . The method of  claim 22 , wherein the original design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances. 
     
     
         29 . The method of  claim 22 , wherein the step of generating the location specific constraints comprises comparing known geometry combinations. 
     
     
         30 . The method of  claim 29 , wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table. 
     
     
         31 . The method of  claim 29 , wherein the step of generating the location specific constraints comprises performing pattern recognition. 
     
     
         32 . The method of  claim 22 , wherein the first area includes interrelated layout objects on one layer. 
     
     
         33 . The method of  claim 32 , wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one interrelated layout object. 
     
     
         34 . The method of  claim 32 , wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent interrelated layout objects. 
     
     
         35 . The method of  claim 34 , wherein the at least two adjacent interrelated layout objects are conductors. 
     
     
         36 . The method of  claim 22 , wherein the step of generating the location specific constraints comprises comparing known geometry combinations. 
     
     
         37 . The method of  claim 22 , wherein the step of generating the location specific constraints comprises using a look-up data table to obtain the location specific constraints using known geometry combinations as a pattern key to search the look-up table. 
     
     
         38 . The method of  claim 22 , wherein the step of generating the location specific constraints comprises performing pattern recognition. 
     
     
         39 . The method of  claim 22 , wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one layout object. 
     
     
         40 . The method of  claim 22 , wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent layout objects. 
     
     
         41 . The method of  claim 22 , wherein:
 the original global design rules comprise a first minimum safeguard distance constraint; and   the step of generating the location specific constraints comprises generating a first additional safeguard distance, and adding the first additional safeguard distance to the first minimum distance to obtain the first location specific constraint.   
     
     
         42 . The method of  claim 22 , wherein application of the original global design rules together with the first location specific constraint in the first area is more restrictive than application of the original global design rules without application of the first location specific constraint in the first area, whereby the modified design layout satisfies the original global design rules. 
     
     
         43 . The method of  claim 22 , further comprising step of applying the original global limits on relative distance between layout objects among the original design layout.