US2018012855A1PendingUtilityA1

Pre-plated substrate for die attachment

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Assignee: NXP USA INCPriority: Apr 7, 2016Filed: Sep 6, 2017Published: Jan 11, 2018
Est. expiryApr 7, 2036(~9.7 yrs left)· nominal 20-yr term from priority
Inventors:David F. AbdoSivanesan A/L Sathiapalan
H10W 90/736H10W 90/734H10W 80/041H10W 72/9415H10W 72/07341H10W 72/07311H10W 72/01935H10W 72/01908H10W 72/01365H10W 72/01335H10W 72/01315H10W 72/952H10W 72/951H10W 72/923H10W 72/355H10W 72/352H10W 72/345H10W 72/344H10W 72/342H10W 72/322H10W 72/321H10W 72/013H10W 99/00H10W 72/073H10W 72/30H10W 72/019H10W 72/90H01L 2224/80048H01L 2224/03019H01L 2924/01079H01L 2224/80359H01L 2224/05568H01L 24/03H01L 2224/03462H01L 2224/05601H01L 2224/05611H01L 2224/0312H01L 2224/80355H01L 2224/05547H01L 2924/1033H01L 2224/05582H01L 24/05H01L 24/80
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Claims

Abstract

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled) 
     
     
         10 . A method of preparing a substrate for attachment to a semiconductor die, the method comprising:
 providing a substrate;   selectively forming an attachment layer on a surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; and   covering the attachment layer with a protective flash plating layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.   
     
     
         11 . The method of  claim 10 , wherein the formation of the attachment layer includes selectively plating one or more attachment stacks to the surface of the substrate at the one or more die attachment locations. 
     
     
         12 . The method of  claim 10 , wherein the formation of the attachment layer includes selectively stamping one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations. 
     
     
         13 . The method of  claim 10 , wherein the formation of the attachment layer includes spot welding one or more attachment preforms at diagonal corners of each of the one or more die attachment locations. 
     
     
         14 . The method of  claim 10 , wherein the formation of the attachment layer includes hot rolling one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations. 
     
     
         15 . The method of  claim 10 , wherein the protective flash plating layer is made from gold. 
     
     
         16 . The method of  claim 10 , wherein the protective flash plating layer has a thickness of about 10 micro-inches or less. 
     
     
         17 . The method of  claim 10 , wherein the attachment layer is made from a combination of gold and tin. 
     
     
         18 . The method of  claim 10 , wherein the substrate is gold plated. 
     
     
         19 . A semiconductor device, comprising:
 a substrate having a surface for attachment to a semiconductor die;   an attachment layer disposed on the surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; and   a protective flash plating layer covering the attachment layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.   
     
     
         20 . The semiconductor device of  claim 19 , wherein:
 the attachment layer comprises gold and tin; and the protective flash plating layer comprises gold.   
     
     
         21 . The semiconductor device of  claim 19 , further comprising:
 one or more attachment preforms stamped onto the surface of the substrate at the one or more die attachment locations.   
     
     
         22 . The semiconductor device of  claim 19 , further comprising:
 one or more attachment stacks plated at the surface of the substrate at the one or more die attachment locations.   
     
     
         23 . The semiconductor device of  claim 19 , further comprising:
 one or more attachment preforms spot welded at diagonal corners of each of the one or more die attachment locations.   
     
     
         24 . The semiconductor device of  claim 19 , further comprising:
 one or more attachment preforms hot rolled onto the surface of the substrate at the one or more die attachment locations.   
     
     
         25 . The semiconductor device of  claim 19 , wherein:
 the substrate surface for attachment to a semiconductor die is gold plated.   
     
     
         26 . The semiconductor device of  claim 19 , wherein:
 the protective flash plating layer has a thickness of about 10 micro-inches or less.   
     
     
         27 . The semiconductor device of  claim 19 , wherein:
 the attachment layer reflow temperature is about 310° C.

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