Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.

We claim: 
     
         1 - 7 . (canceled) 
     
     
         8 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first insulating layer and a second insulating layer on a substrate to which an interlayer insulating layer including a lower contact is provided;   forming an interconnection contact hole in the second insulating layer, the interconnection contact hole positioned over the lower contact to vertically overlap the lower contact;   forming a mask layer having an opening on the first insulating layer, the opening vertically overlapping the lower contact;   etching the first insulating layer exposed by the opening to form a contact hole exposing the lower contact;   removing the mask layer; and   forming an interconnection structure contacting the lower contact in the contact hole and the interconnection contact hole.   
     
     
         9 . The method of  claim 8 , wherein the forming the contact hole comprises etching a part of the first insulating layer exposed by the opening and the interconnection contact hole at the same time. 
     
     
         10 . The method of  claim 8 , further comprising forming a hard mask pattern on the second insulating layer before forming the interconnection contact hole,
 wherein the hard mask pattern is formed so that the second insulating layer over the lower contact is exposed.   
     
     
         11 . The method of  claim 8 , wherein the contact hole is formed to vertically overlap the interconnection contact hole. 
     
     
         12 . The method of  claim 8 , wherein the forming the interconnection structure comprises:
 forming a conductive layer filling the contact hole and the interconnection contact hole on the second insulating layer; and   performing a polishing process on the conductive layer until a top surface of the second insulating layer is exposed.   
     
     
         13 . The method of  claim 8 , wherein the interconnection structure comprises an upper contact and a metal interconnection,
 wherein the upper contact is formed in the contact hole to contact the lower contact and the metal interconnection is formed in the interconnection contact hole.   
     
     
         14 . The method of  claim 8 , wherein the forming the interconnection structure comprises forming an upper contact and a metal interconnection,
 wherein the upper contact is formed in the contact hole at the same time when the metal interconnection is formed in the interconnection contact hole to be self-aligned on the lower contact.   
     
     
         15 . A method of manufacturing a semiconductor device, the method comprising:
 forming an insulating layer on a substrate;   forming a plurality of holes in an upper portion of the insulating layer;   forming a mask layer having openings exposing at least a set of the plurality of holes;   etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes; and   forming a conductive structure in the through hole.   
     
     
         16 . The method of  claim 15 , wherein the insulating layer is formed of a plurality of layers and the upper portion includes at least one layer of the plurality of layers. 
     
     
         17 . The method of  claim 15 , wherein the conductive structure contacts a contact structure formed below the through hole. 
     
     
         18 . The method of  claim 17 , wherein the contact structure is electrically coupled to a region comprising silicon or germanium. 
     
     
         19 . The method of  claim 18 , wherein the region comprising silicon or germanium is a source/drain region of a field effect transistor. 
     
     
         20 . The method of  claim 15 , wherein the forming the plurality of holes comprises:
 forming a hard mask layer on the insulating layer;   forming a sacrificial pattern on the hard mask layer;   forming a spacer layer conformally covering the sacrificial pattern and the hard mask layer;   removing a portion of the spacer layer to form spacers exposing the upper surface of the sacrificial pattern and a portion of the hard mask layer;   removing the sacrificial pattern;   removing a portion of the hard mask layer using the spacers as an etch mask to form a mask pattern; and   removing an upper portion of the insulating layer to form the plurality holes using the mask pattern as an etch mask.