System and method for a cache in a multi-core processor

Abstract

The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

1 . A method for operating a data processing system, the method comprising:
 reading data executed within a first task based on a first processor core instruction;   setting a lock limiting further access to the data executed within the first task based on the first processor core instruction;   writing the data executed within the first task based on a second processor core instruction;   releasing the lock based on the second processor core instruction; and   rejecting access to the data executed within the first task by one or more other tasks while the lock is set,   the first processor core instruction and the second processor core instruction being executed by at least one of a plurality of processor cores of the data processing system, a data memory structure being connected to the plurality of processor cores, the data memory structure including:
 one or more dedicated Level-1 data caches provided in each of the plurality of processor cores, and 
 a combined memory hierarchy connected to the one or more dedicated Level-1 data caches, the combined memory hierarchy having one or more shared higher level caches and a main memory. 
   
     
     
         2 . The method of  claim 1  wherein the one or more shared higher level caches include a plurality of higher level caches arranged in a tree structure. 
     
     
         3 . The method of  claim 1  wherein the one or more shared higher level caches include a plurality of higher level caches arranged in a ring structure. 
     
     
         4 . The method of  claim 1  wherein setting the lock includes transmitting a thread identification to the data memory structure, the thread identification identifying at least one thread executed by one or more of the processor cores. 
     
     
         5 . The method of  claim 1  wherein locking information to implement the lock is part of a cache tag. 
     
     
         6 . The method of  claim 1  wherein locking information to implement the lock is stored as tag information within the data memory structure. 
     
     
         7 . The method of  claim 1  wherein the tag information in the data memory structure is attached to data that is at least one of:
 stored in the data memory structure; and 
 transmitted in the data memory structure. 
 
     
     
         8 . The method of  claim 1  wherein the tag information in the data memory structure is attached to a variable that is at least one of:
 stored in the data memory structure; and 
 transmitted in the data memory structure. 
 
     
     
         9 . A method for operating a data processing system, comprising:
 retrieving a thread for execution by at least one processor core of a plurality of processor cores connected to a data memory structure, wherein the data memory structure includes:
 one or more dedicated Level-1 data caches included in each of the plurality of processor cores, and 
 a combined memory hierarchy connected to the one or more dedicated Level-1 data caches, the combined memory hierarchy having one or more shared higher level caches and a main memory; 
   executing the thread, including associating tag information with data transmitted within the data memory structure, wherein the tag information includes information configured to implement a lock for the data associated with the tag information; and   managing, based on the tag information, at least one of:
 transmission of the data within the combined memory hierarchy, and 
 transmission of the data between the combined memory hierarchy and one or more of the processor cores. 
   
     
     
         10 . The method of  claim 9  wherein the one or more shared higher level caches include a plurality of higher level caches arranged in one of a tree structure and a ring structure. 
     
     
         11 . The method of  claim 9  wherein the tag information is stored in respective Level-1 data caches of the one or more dedicated Level-1 data caches. 
     
     
         12 . The method of  claim 9  wherein the one or more shared higher level caches are at a level above the one or more dedicated Level-1 data caches. 
     
     
         13 . The method of  claim 9  wherein the tag information is attached to data that is at least one of:
 stored in the data memory structure; and 
 transmitted in the data memory structure. 
 
     
     
         14 . The method of  claim 9  wherein the tag information is attached to a variable that is at least one of:
 stored in the data memory structure; and 
 transmitted in the data memory structure. 
 
     
     
         15 . The method of  claim 9  wherein the tag information is located within a descriptor table. 
     
     
         16 . The method of  claim 9  wherein the tag information defines a positioning of the associated data in the data memory structure, wherein the positioning indicates one of:
 one or more of the at least one dedicated level-1 cache, 
 one or more of the at least one shared higher level cache, and 
 the main memory. 
 
     
     
         17 . The method of  claim 9  wherein the tag information defines at least one of:
 a movement of the associated data in the data memory structure between the one or more shared higher level caches of the combined memory hierarchy; 
 duplication of the associated data in the data memory structure; 
 access to associated data stored in the data memory structure; and 
 an ownership of the associated data by one or more threads executed on one or multiple of the processor cores. 
 
     
     
         18 . The method of  claim 9  wherein the tag information indicates at least one of:
 which of the plurality of processor cores owns the associated data; 
 that the associated data is read-only; 
 that the associated data can be duplicated; 
 that the associated data is more frequently read from the data memory structure than written to the data memory structure; 
 that the associated data is more frequently written to the data memory structure than read from the data memory structure; 
 that associated data is written to the data memory structure and read from the data memory structure with approximately equal occurrence; 
 that data associated with the tag information is written by a single source thread and read by a plurality of threads; and 
 that the data associated with the tag information is randomly accessed by one or multiple of the processor cores. 
 
     
     
         19 . A data processing system comprising:
 a plurality of processor cores; and   a data memory structure connected to the plurality of processor cores, the data memory structure including:   one or more dedicated Level-1 data caches included in each of the plurality of processor cores; and   a combined memory hierarchy connected to the one or more dedicated Level-1 data caches, the combined memory hierarchy having one or more shared higher level caches and a main memory,   wherein at least one of the plurality of processor cores is configured to execute:
 a first processor core instruction configured to read data executed within a first task and configured to set a lock limiting further access to the data executed within the first task; and 
 a second processor core instruction configured to write the data executed within the first task and configured to release the lock, 
 the lock being configured to reject access to the data executed within the first task by one or more other tasks while the lock is set. 
   
     
     
         20 . The data processing system of  claim 19  wherein the first processor core instruction is configured to set the lock that includes transmitting a thread identification to the data memory structure, the thread identification identifying at least one thread executed by one or more of the processor cores.