US2018061975A1PendingUtilityA1

Nitride semiconductor device and nitride semiconductor package

Assignee: ROHM CO LTDPriority: Aug 24, 2016Filed: Aug 22, 2017Published: Mar 1, 2018
Est. expiryAug 24, 2036(~10.1 yrs left)· nominal 20-yr term from priority
H10W 90/756H10W 90/736H10W 74/00H10W 72/07554H10W 72/884H10W 72/547H10W 74/129H10W 70/481H01L 23/3114H01L 29/205H01L 29/2003H01L 29/66462H01L 23/49562H01L 29/7787H01L 29/475H10D 64/667H10D 64/602H10D 64/256H10D 64/111H10D 64/62H10D 62/343H10D 64/64H10D 62/8503H10D 62/824H10D 62/85H10D 30/6738H10D 30/675H10D 30/475H10D 30/015H10D 30/4755
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): d G  2   E F  q  ( N DA + N A - N DD - N D ) ɛ 0  ɛ C + Φ B - d B  P ɛ 0  ɛ B > 0 ( 1 )

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A nitride semiconductor device comprising:
 an electron transit layer;   an electron supply layer, in contact with the electron transit layer and constituted of a nitride semiconductor composition differing from that of the electron transit layer;   a gate layer, formed selectively on the electron supply layer and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity; and   a gate electrode, formed on the gate layer, and   wherein the following formula (1) is satisfied:   
       
         
           
             
               
                 
                   
                     
                       
                         
                           d 
                           G 
                         
                          
                         
                           
                             
                               2 
                                
                               
                                   
                               
                                
                               
                                 E 
                                 F 
                               
                                
                               
                                 q 
                                  
                                 
                                   ( 
                                   
                                     
                                       N 
                                       DA 
                                     
                                     + 
                                     
                                       N 
                                       A 
                                     
                                     - 
                                     
                                       N 
                                       DD 
                                     
                                     - 
                                     
                                       N 
                                       D 
                                     
                                   
                                   ) 
                                 
                               
                             
                             
                               
                                 ɛ 
                                 0 
                               
                                
                               
                                 ɛ 
                                 C 
                               
                             
                           
                         
                       
                       + 
                       
                         Φ 
                         B 
                       
                       - 
                       
                         
                           
                             d 
                             B 
                           
                            
                           P 
                         
                         
                           
                             ɛ 
                             0 
                           
                            
                           
                             ɛ 
                             B 
                           
                         
                       
                     
                     > 
                     0 
                   
                 
                 
                   
                     ( 
                     1 
                     ) 
                   
                 
               
             
           
         
         with the definitions of the respective symbols in the formula (1) being as follows. 
         d G : thickness (cm) of the gate layer 
         d B : thickness (cm) of the electron supply layer 
         P: polarization (C/cm 2 ) of the electron supply layer 
         q: elementary charge (C) 
         Φ B : work function (eV) of the gate electrode−electron affinity (3.6 eV) of GaN 
         N DA +N A −N DD −N D : effective acceptor concentration of the electron transit layer 
         ε C : relative permittivity of the electron transit layer 
         ε B : relative permittivity of the electron supply layer 
         ε 0 : permittivity of vacuum 
         E F : energy difference (eV) between a Fermi level and a lower end of a conduction band (E C ) of the electron transit layer 
       
     
     
         2 . The nitride semiconductor device according to  claim 1 , wherein the electron transit layer and the gate layer contain GaN and
 the electron supply layer contains AlGaN.   
     
     
         3 . The nitride semiconductor device according to  claim 1 , wherein the effective acceptor concentration N DA +N A −N DD −N D  of the electron transit layer is not less than 5×10 16  cm −3 ,
 the thickness d G  of the gate layer is not less than 80 nm, 
 an Al composition of the electron supply layer is not more than 25%, and 
 the thickness d B  of the electron supply layer is not more than 20 nm. 
 
     
     
         4 . The nitride semiconductor device according to  claim 1 , wherein the electron transit layer contains Mg in a region with 150 nm from an interface with the electron supply layer. 
     
     
         5 . The nitride semiconductor device according to  claim 1 , wherein the electron transit layer contains Mg as a deep acceptor. 
     
     
         6 . The nitride semiconductor device according to  claim 1 , wherein the electron transit layer contains C as a deep acceptor. 
     
     
         7 . The nitride semiconductor device according to  claim 1 , wherein that the gate layer effectively does not contain an acceptor type impurity signifies that a concentration of the acceptor type impurity in the gate layer is less than 1×10 17  cm −3 . 
     
     
         8 . The nitride semiconductor device according to  claim 7 , wherein the concentration of the acceptor type impurity in the gate layer is less than 1×10 16  cm −3 . 
     
     
         9 . A nitride semiconductor device comprising:
 an electron transit layer, constituted of a nitride semiconductor;   an electron supply layer, constituted of Al x Ga 1−x N (x≦1) on the electron transit layer;   a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer; and   a gate electrode formed on the gate layer; and   wherein the Al composition x of the electron supply layer is such that x≧0.3.   
     
     
         10 . The nitride semiconductor device according to  claim 9 , wherein a thickness of the electron supply layer is not more than 10 nm. 
     
     
         11 . The nitride semiconductor device according to  claim 9 , wherein the Al composition x of the electron supply layer is such that x=1. 
     
     
         12 . The nitride semiconductor device according to  claim 9 , further comprising: an etching stop layer, constituted of Al x′ Ga 1−x′ N (x′≦1) on the electron supply layer; and
 wherein a relationship x<x′ holds between the electron supply layer and the etching stop layer. 
 
     
     
         13 . The nitride semiconductor device according to  claim 12 , wherein the electron supply layer includes an AlN electron supply layer and
 the Al composition x′ of the etching stop layer is such that 0.1≦x′≦0.2.   
     
     
         14 . The nitride semiconductor device according to  claim 13 , wherein the electron supply layer includes an AlN electron supply layer with a thickness of not more than 2 nm,
 the etching stop layer has a thickness of not more than 10 nm, and   the Al composition x′ of the etching stop layer is such that x′=0.1.   
     
     
         15 . The nitride semiconductor device according to  claim 13 , comprising: a source electrode and a drain electrode disposed to sandwich the gate electrode; and
 wherein portions or entireties of the electron supply layer and the etching stop layer are removed selectively in formation regions of the source electrode and the drain electrode.   
     
     
         16 . A nitride semiconductor device comprising:
 an electron transit layer, constituted of a nitride semiconductor;   an electron supply layer, constituted of Al x In y Ga 1−x−y N (1≧x+y) on the electron transit layer;   a gate layer, constituted of a nitride semiconductor formed selectively on the electron supply layer; and   a gate electrode formed on the gate layer; and   wherein the Al composition x of the electron supply layer is such that x≧0.3 and the In composition y of the electron supply layer is such that 0.02≧y≧0.   
     
     
         17 . The nitride semiconductor device according to  claim 9 , wherein the electron transit layer contains Mg as an impurity. 
     
     
         18 . The nitride semiconductor device according to  claim 17 , wherein a concentration of Mg in the electron transit layer is not less than 1×10 16  cm −3  and not more than 1×10 17  cm −3 . 
     
     
         19 . The nitride semiconductor device according to  claim 1 , wherein the gate electrode contains Ni, Pt, Mo, W, or TiN. 
     
     
         20 . A nitride semiconductor package comprising:
 the nitride semiconductor device according to  claim 1 ;   a terminal frame, on which the nitride semiconductor device is installed; and   a resin package, sealing the nitride semiconductor device and the terminal frame.

Join the waitlist — get patent alerts

Track US2018061975A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.