Self-biasing and self-sequencing of depletion-mode transistors

Abstract

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

What is claimed is: 
     
         1 . A transistor circuit comprising:
 a transistor having a gate terminal and first and second conduction terminals;   a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor;   a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage; and   a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage;   wherein the first circuit, the second circuit, and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the first voltage is applied to the first conduction terminal of the transistor.   
     
     
         2 . (canceled) 
     
     
         3 . The transistor circuit as defined in  claim 1 , wherein the transistor comprises a depletion mode transistor. 
     
     
         4 . The transistor circuit as defined in  claim 3 , wherein the gate bias voltage is negative and the first voltage is positive. 
     
     
         5 . The transistor circuit as defined in  claim 4 , wherein the first circuit comprises an RF coupler, a rectifier and a voltage regulator. 
     
     
         6 . The transistor circuit as defined in  claim 5 , wherein the rectifier comprises a diode rectifier. 
     
     
         7 . The transistor circuit as defined in  claim 5 , wherein the rectifier comprises a half bridge rectifier. 
     
     
         8 . The transistor circuit as defined in  claim 5 , wherein the rectifier comprises a full bridge rectifier. 
     
     
         9 . The transistor circuit as defined in  claim 5 , wherein the voltage regulator comprises a Zener diode. 
     
     
         10 . The transistor circuit as defined in  claim 5 , wherein the RF coupler comprises a directional coupler. 
     
     
         11 . The transistor circuit as defined in  claim 5 , wherein the second circuit comprises an RF coupler and a rectifier. 
     
     
         12 . The transistor circuit as defined in  claim 5 , wherein the transistor comprises a gallium nitride depletion mode power transistor. 
     
     
         13 . A method for operating a transistor having a gate terminal and first and second conduction terminals, comprising:
 converting an AC input signal to a gate bias voltage and applying the gate bias voltage to the gate terminal of the transistor;   converting the AC input signal to a control voltage; and   after applying the gate bias voltage to the gate terminal of the transistor, applying a first voltage to the first conduction terminal of the transistor in response to the control voltage.   
     
     
         14 . (canceled) 
     
     
         15 . The method as defined in  claim 13 , wherein the transistor comprises a gallium nitride depletion mode power transistor, wherein the gate bias voltage applied to the gate terminal of the transistor is negative and wherein the first voltage applied to the first conduction terminal of the transistor is positive. 
     
     
         16 . A transistor circuit comprising:
 a depletion mode RF power transistor having a gate terminal, a drain terminal and a source terminal;   a first circuit configured to convert an input RF signal to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor;   a second circuit configured to convert the RF input signal to a control voltage; and   a switching circuit configured to apply a drain voltage to the drain terminal of the transistor in response to the control voltage, wherein the first and second circuits and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the drain voltage is applied to the drain terminal of the transistor.   
     
     
         17 . The transistor circuit as defined in  claim 17 , wherein the gate bias voltage is negative and the drain voltage is positive. 
     
     
         18 . The transistor circuit as defined in  claim 17 , wherein the first circuit comprises an RF coupler, a rectifier and a voltage regulator. 
     
     
         19 . The transistor circuit as defined in  claim 18 , wherein the second circuit comprises an RF coupler and a rectifier.