Wafer stacking to form a multi-wafer-bonded structure

Abstract

In one aspect, a method includes heating a wafer chuck, heating a first wafer, depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck, spinning the wafer chuck to spread the first epoxy at least partially across the first wafer, placing a second wafer on the first epoxy disposed on the first wafer and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure.

What is claimed is: 
     
         1 - 15 . (canceled) 
     
     
         16 . A multi-wafer-bonded stack, comprising:
 a first wafer having a first surface; and   a second wafer having a first surface bonded to the first surface of the first wafer by a first epoxy, wherein the first epoxy covers an entirety of the first surface of the first wafer and an entirety of the first surface of the second wafer,   wherein the first epoxy is free of voids.   
     
     
         17 . The multi-wafer-bonded stack of  claim 16 , further comprising a third wafer bonded to the first wafer by a second epoxy,
 wherein the second epoxy is free of voids.   
     
     
         18 . The multi-wafer-bonded stack of  claim 17 , wherein the first wafer is one of a controlled expansion (CE) wafer, a stainless steel wafer or a titanium wafer, and
 wherein the second wafer is a readout integrated circuit (ROIC) wafer.   
     
     
         19 . The multi-wafer-bonded stack of  claim 18 , wherein the third wafer is silicon. 
     
     
         20 . The multi-wafer-bonded stack of  claim 18 , wherein the ROIC wafer comprises indium bumps. 
     
     
         21 . The multi-wafer-bonded stack of  claim 17 , wherein the first epoxy and the second epoxy can withstand cryogenic temperatures of −150° C. or less. 
     
     
         22 . A multi-wafer-bonded stack, comprising:
 a first wafer having a first surface and a second surface, wherein the first wafer is one of a controlled expansion (CE) wafer, a stainless steel wafer or a titanium wafer;   a second wafer having a first surface bonded to the first surface of the first wafer by a first epoxy, wherein the second wafer is a readout integrated circuit (ROIC) wafer; and   a third wafer having a first surface bonded to the second surface of the first wafer by a second epoxy,   wherein the first epoxy is free of voids, wherein the first epoxy covers an entirety of the first surface of the first wafer and an entirety of the first surface of the second wafer, and   wherein the second epoxy is free of voids, wherein the second epoxy covers an entirety of the first surface of the third wafer and an entirety of the second surface of the first wafer.   
     
     
         23 . The multi-wafer-bonded stack of  claim 22 , wherein the third wafer is silicon. 
     
     
         24 . The multi-wafer-bonded stack of  claim 22 , wherein the ROIC wafer comprises indium bumps. 
     
     
         25 . The multi-wafer-bonded stack of  claim 22 , wherein the first epoxy and the second epoxy can withstand cryogenic temperatures of −150° C. or less.