Semiconductor device and semiconductor package

Abstract

Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a substrate including a conductive layer;   an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer; and   an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening,   wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess.   
     
     
         2 . The semiconductor package of  claim 1 , wherein a sidewall portion and a bottom portion of the at least one recess in the insulating layer are an integrated single body. 
     
     
         3 . The semiconductor package of  claim 2 , wherein the sidewall portion and the bottom portion of the at least one recess do not have an interface therebetween. 
     
     
         4 . The semiconductor package of  claim 1 , wherein a sidewall of a sidewall portion of the at least one recess is substantially perpendicular to an upper surface of the insulating layer. 
     
     
         5 . The semiconductor package of  claim 1 , wherein a width of the at least one recess in a horizontal direction increases in a direction towards a bottom of the at least one recess. 
     
     
         6 . The semiconductor package of  claim 5 , wherein the at least one recess substantially surrounds the opening. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the at least one recess includes at least a micro-recess. 
     
     
         8 . The semiconductor package of  claim 1 , wherein a sidewall of a sidewall portion of the at least one recess includes consecutive scallops in a substantially vertical direction. 
     
     
         9 . The semiconductor package of  claim 1 , wherein the at least one recess comprises a first recess extending in a first direction and surrounding the opening, and a second recess extending in a second direction and surrounding the opening. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the under-bump metal layer is electrically connected to the conductive layer through a via, and a depth of the at least one recess is smaller than a height of the via. 
     
     
         11 . The semiconductor package of  claim 1 , wherein a sidewall of the opening is substantially perpendicular to an upper surface of the insulating layer. 
     
     
         12 . The semiconductor package of  claim 1 , wherein the substrate includes a mounting area in which a semiconductor die is mounted, and a peripheral area in which a semiconductor chip is not mounted, and the opening is in the peripheral area. 
     
     
         13 . A semiconductor device comprising:
 a semiconductor chip including a conductive layer;   an insulating layer including at least one trench in an upper surface thereof, the insulating layer exposing at least part of the conductive layer;   an under-bump metal layer electrically connected to the conductive layer, the under-bump metal layer at least partially filling the at least one trench; and   a solder bump on the under-bump metal layer,   wherein the at least one trench has a sidewall and a bottom, the sidewall and the bottom of the at least one trench are an integrated single body, and the at least one trench at least partially has a substantially constant width region or a constantly narrowing width region in a direction towards the bottom of the at least one trench.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the under-bump metal layer is electrically connected to the conductive layer through a via in an opening of the insulating layer, and a height of the at least one trench is about 10% to about 90% of a height of the opening. 
     
     
         15 . The semiconductor device of  claim 14 , wherein an upper surface of the under-bump metal layer is substantially planar in a region outside the opening. 
     
     
         16 . A semiconductor device, comprising:
 a substrate including a conductive layer;   an insulating layer including at least one trench at an upper surface thereof and an opening exposing at least part of the conductive layer; and   an under-bump conductive metal layer filling the at least one trench and at least part of the opening;   the at least one trench being configured to at least reduce crack propagation through the substrate.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising:
 a solder bump on the under-bump conductive metal layer.   
     
     
         18 . The semiconductor device of  claim 16 , wherein the at least one trench defines a perimeter around the opening. 
     
     
         19 . The semiconductor device of  claim 18 , wherein the at least one trench has one of a substantially constant width region and a varying width region in a direction towards a bottom thereof. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the trench is adjacent to the opening.