Dynamic configuration of input/output controller access lanes

Abstract

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

1 - 26 . (canceled) 
     
     
         27 . A System-on-a-Chip (SoC) comprising:
 a plurality of Input/Output (I/O) controllers;   a plurality of lanes;   a lane mapping module to multiplex at least one of said I/O controllers to at least one of said lanes based on a configuration;   a first processor to detect a change request, said change request to modify said configuration from an existing configuration to a new configuration; and   a second processor to: verify that said new configuration is valid based on a stock keeping unit (SKU) associated with said SoC; and, if said verification is successful, store said new configuration in non-volatile memory and reset said SoC.   
     
     
         28 . The system of  claim 27 , wherein said configuration comprises an I/O controller to lane mapping, a lane enablement selection or a lane width. 
     
     
         29 . The system of  claim 27 , wherein said I/O controllers load said new configuration from said non-volatile memory, after said reset. 
     
     
         30 . The system of  claim 27 , wherein said verification of said new configuration further comprises verifying an I/O controller to lane mapping, verifying a lane enablement selection and verifying a lane width. 
     
     
         31 . The system of  claim 27 , wherein said change request detection is performed during a power state transition of said SoC from a lower power state to a higher power state. 
     
     
         32 . The system of  claim 27 , wherein said change request is received from an agent external to said SoC. 
     
     
         33 . The system of  claim 27 , wherein said first processor is to execute a Basic Input Output System (BIOS). 
     
     
         34 . The system of  claim 27 , wherein said second processor is a management engine microcontroller. 
     
     
         35 . The system of  claim 27 , wherein said plurality of Input/Output (I/O) controllers comprise a Peripheral Component Interconnect Express (PCIe) controller, a Universal Serial Bus (USB) controller and/or a Serial Advanced Technology Attachment (SATA) controller. 
     
     
         36 . At least one computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for configuration of Input/Output (I/O) controller lane access of a system, said operations comprising:
 detecting a change request, said change request to modify said configuration from an existing configuration to a new configuration;   verifying that said new configuration is valid based on a stock keeping unit (SKU) associated with said system; and   if said verification is successful, storing said new configuration in non-volatile memory and resetting said system.   
     
     
         37 . The computer-readable storage medium of  claim 36 , wherein said configuration comprises an I/O controller to lane mapping, a lane enablement selection or a lane width. 
     
     
         38 . The computer-readable storage medium of  claim 36 , further comprising providing said new configuration to said I/O controllers from said non-volatile memory, after resetting said system. 
     
     
         39 . The computer-readable storage medium of  claim 36 , wherein said verifying further comprises verifying an I/O controller to lane mapping, verifying a lane enablement selection and verifying a lane width. 
     
     
         40 . The computer-readable storage medium of  claim 39 , further comprising, if said verification fails, signaling an error. 
     
     
         41 . The computer-readable storage medium of  claim 36 , wherein said change request detection is performed during a power state transition of said system from a lower power state to a higher power state. 
     
     
         42 . The computer-readable storage medium of  claim 36 , wherein said change request detection is performed by a Basic Input Output System (BIOS). 
     
     
         43 . The computer-readable storage medium of  claim 36 , further comprising receiving said change request from an agent external to said system. 
     
     
         44 . A method for configuration of Input/Output (I/O) controller lane access of a system, said method comprising:
 detecting a change request, said change request to modify said configuration from an existing configuration to a new configuration;   verifying that said new configuration is valid based on a stock keeping unit (SKU) associated with said system; and   if said verification is successful, storing said new configuration in non-volatile memory and resetting said system.   
     
     
         45 . The method of  claim 44 , wherein said configuration comprises an I/O controller to lane mapping, a lane enablement selection or a lane width. 
     
     
         46 . The method of  claim 44 , further comprising providing said new configuration to said I/O controllers from said non-volatile memory, after resetting said system. 
     
     
         47 . The method of  claim 44 , wherein said verifying further comprises verifying an I/O controller to lane mapping, verifying a lane enablement selection and verifying a lane width. 
     
     
         48 . The method of  claim 47 , further comprising, if said verification fails, signaling an error. 
     
     
         49 . The method of  claim 44 , wherein said change request detection is performed during a power state transition of said system from a lower power state to a higher power state. 
     
     
         50 . The method of  claim 44 , wherein said change request detection is performed by a Basic Input Output System (BIOS). 
     
     
         51 . The method of  claim 44 , further comprising receiving said change request from an agent external to said system. 
     
     
         52 . The method of  claim 44 , further comprising generating said change request on a processor of said system.