Apparatus and method for optimized tile-based rendering

Abstract

A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

What is claimed is: 
     
         1 . An apparatus comprising:
 a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data;   a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers;   spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and   a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.   
     
     
         2 . The apparatus as in  claim 1  wherein the off-chip memory comprises a system memory. 
     
     
         3 . The apparatus as in  claim 2  wherein a separate pointer buffer is managed for each tile to be processed by the TBIMR module. 
     
     
         4 . The apparatus as in  claim 3  further comprising:
 a write pointer to be updated responsive to the spill circuitry spilling the additional geometry data to the off-chip memory. 
 
     
     
         5 . An apparatus comprising:
 a geometry processing circuit of a tile-based immediate mode rendering (TBIMR) pipeline to perform geometric processing operations on sets of triangles, each subset of triangles associated with a tile of an image frame and each tile having a plurality of sub-tiles, the geometry processing circuit comprising a bounding box processing module to grow a bounding box to include each triangle in the set of triangles, wherein when all of the set of triangles have been processed, a first bounding box has been generated to include all of the triangles;   a pixel processing circuit to receive the first bounding box, the pixel processing circuit including:   a depth buffer to store depth data; and   an occlusion testing and culling module to occlusion test the first bounding box by comparing it with the depth data stored within the depth buffer, the depth data comprising a minimum depth value and a maximum depth value for each sub-tile, wherein:   if the first bounding box has a maximum depth value which is smaller than all of the minimum depth values of the sub-tiles, then the set of triangles in the first bounding box are passed to remaining pixel processing stages and flagged as visible;   if the first bounding box has a minimum depth value which is greater than all of the maximum depth values of the sub-tiles, then first set of triangles in the first bounding box are discarded.   
     
     
         6 . The apparatus as in  claim 5  wherein if the first bounding box has a maximum depth value which is smaller than all of the minimum depth values of the sub-tiles, then no additional depth buffer testing is performed in the remaining pixel processing stages until the pixels have been overwritten. 
     
     
         7 . The apparatus as in  claim 6  wherein the occlusion testing and culling module is to set N bits per sub-tile to indicate status of the first bounding box relative to the sub-tiles. 
     
     
         8 . The apparatus as in  claim 7  wherein N=2 and wherein the status is defined by a first value to indicate that the first bounding box is fully visible with respect to the sub-tile, a second value to indicate that the first bounding box is fully occluded with respect to the sub-tile, and a third value to indicate that the first bounding box is ambiguous with respect to the sub-tile. 
     
     
         9 . The apparatus as in  claim 7  wherein the pixel processing circuit checks the N bits before initiating depth buffer testing for each sub-tile, wherein if the two bits indicate that the first bounding box is fully occluded with respect to a first sub-tile, then triangle processing is terminated but only for the first sub-tile, if the two bits indicate that the first bounding box is fully visible, then triangle processing proceeds. 
     
     
         10 . The apparatus as in  claim 8  wherein the first bounding box is a 2D bounding box which the occlusion testing and culling module tests against all sub-tiles that overlap the 2D bounding box. 
     
     
         11 . An apparatus comprising:
 a tile-based immediate mode renderer to render a plurality of tiles for each image frame;   a selective frame buffer update module to selectively update specified tiles in each successive image frame in accordance with tile update rules; and   a tile blending module to combine values from a current tile in a current frame with values from the tile in a prior frame to generate a blended tile, the blended tile to be displayed in the current frame.   
     
     
         12 . The apparatus as in  claim 11  wherein the update rules specify that the selective frame buffer update module is to update those tiles which have changed most significantly between frames. 
     
     
         13 . The apparatus as in  claim 11  wherein the update rules specify that the selective frame buffer update module is to update N tiles in each new image frame. 
     
     
         14 . The apparatus as in  claim 13  wherein each image frame includes M tiles where M>N and wherein the M tiles in each new image frame on a round-robin basis. 
     
     
         15 . The apparatus as in  claim 11  wherein the tile blending module is to combine new data for a first tile with data for the first tile from the prior frame which has been stored in a memory/storage device. 
     
     
         16 . The apparatus as in  claim 15  wherein the tile blending module is to determine the blended tile using α*[new tile data]+(1−α)*[old tile data] where α is selected to be between 0 and 1.