Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes a gate insulating film on a semiconductor substrate, a memory cell array in a memory cell region, a first transistor in a peripheral circuit region which surrounds the memory cell region, a second transistor in a scribe region which surrounds the peripheral circuit region, a first stepped structure in the memory cell region, a second stepped structure in the peripheral circuit region facing the first stepped structure, and an interlayer insulating film between the first and second stepped structures. Each of the first and second stepped structures includes a plurality of insulating layers and conductive layers that are alternately stacked on the semiconductor substrate, and an upper surface of an uppermost layer of the first stepped structure, an upper surface of an uppermost layer of the second stepped structure, and an upper surface of the interlayer insulating film are formed on the same plane.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a semiconductor substrate having a main surface;   a gate insulating film which covers the main surface of the semiconductor substrate;   a memory cell array disposed in a memory cell region;   a first transistor disposed in a peripheral circuit region which surrounds the memory cell region, the first transistor having a first gate electrode on the gate insulating film;   a second transistor disposed in a scribe region which surrounds the peripheral circuit region, the second transistor having a second gate electrode on the gate insulating film;   a first stepped structure disposed in the memory cell region and a second stepped structure disposed in the peripheral circuit region, the first and second stepped structures facing each other and each including a plurality of insulating layers and conductive layers that are alternately stacked on the main surface of the semiconductor substrate; and   an interlayer insulating film disposed in a region where the first stepped structure and the second stepped structure face each other, wherein   an upper surface of an uppermost layer of the first stepped structure, an upper surface of an uppermost layer of the second stepped structure, and an upper surface of the interlayer insulating film are formed on the same plane.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein
 the first stepped structure has a lowermost layer that extends in a first direction towards the second stepped structure more than the uppermost layer of the first stepped structure, and   the second stepped structure has a lowermost layer that extends in a second direction towards the first stepped structure more than the uppermost layer of the second stepped structure,   the first and second directions being opposite directions.   
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein
 the first stepped structure has middle layers that extend in the first direction towards the second stepped structure more than the uppermost layer of the first stepped structure but less than the lowermost layer of the first stepped structure, and   the second stepped structure has middle layers that extend in the second direction towards the first stepped structure more than the uppermost layer of the second stepped structure but less than the lowermost layer of the second stepped structure.   
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein the scribe region extends in a third direction that is parallel to the main surface of the semiconductor substrate and perpendicular to the first and second directions. 
     
     
         5 . The semiconductor memory device according to  claim 4 , wherein the second gate electrode extends in the third direction. 
     
     
         6 . The semiconductor memory device according to  claim 1 , further comprising:
 a first stacked structure in the scribe region including a plurality of insulating layers and conductive layers that are alternately stacked above the second gate electrode; and   a second stacked structure in the peripheral circuit region including a plurality of insulating layers and conductive layers that are alternately stacked above the first gate electrode.   
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein
 the number of stacked layers in each of the first stacked structure and the second stacked structure is fewer than the number of stacked layers in either the first stepped structure or the second stepped structure.   
     
     
         8 . The semiconductor memory device according to  claim 6 , wherein the conductive layers of the first stacked structure are electrically connected to the conductive layers in the second stacked structure, respectively. 
     
     
         9 . The semiconductor memory device according to  claim 6 , wherein the conductive layers of the second stacked structure are each electrically connected to one of the conductive layers in the second stepped structure. 
     
     
         10 . The semiconductor memory device according to  claim 9 , wherein the uppermost conductive layer of the second stepped structure is not electrically connected to any of the conductive layers in the second stacked structure. 
     
     
         11 . The semiconductor memory device according to  claim 9 , wherein the two uppermost conductive layers of the second stepped structure are not electrically connected to any of the conductive layers in the second stacked structure. 
     
     
         12 . A method of manufacturing a semiconductor memory device comprising:
 forming a gate insulating film on a main surface of a semiconductor substrate;   forming a first transistor in a peripheral circuit region which surrounds a memory cell region and a second transistor in a scribe region which surrounds the peripheral circuit region, on an upper surface of the gate insulating film, the first transistor having a first gate electrode on the gate insulating film, and the second transistor having a second gate electrode on the gate insulating film;   alternately stacking a plurality of insulating layers and sacrificial insulating layers to form a multi-layered insulation body on the upper surface of the gate insulating film, the first transistor, and the second transistor;   removing at least an upper portion of the multi-layered insulation body formed in the scribe region to form a first multi-layered portion disposed above the second transistor, causing a height from the upper surface of the gate insulating film to an upper surface of the first multi-layered portion to be equal to a height from the upper surface of the gate insulating film to an upper surface of a second multi-layered portion of the multi-layered insulation body disposed in the memory cell region;   etching a first region positioned at an end portion of the memory cell region, a second region positioned in the peripheral circuit region and configured to face the first region in a direction perpendicular to an extending direction of the scribe region, and an area positioned between the first region and the second region to form a first stepped structure at the end portion of the memory cell region which extends from the upper surface of the multi-layered insulation body to the upper surface of the gate insulating film, a second stepped structure in the peripheral circuit region, which extends from an upper surface of the multi-layered insulation body to the upper surface of the gate insulating film and faces the first stepped structure, and a recessed portion disposed between the first stepped structure and the second stepped structure;   forming an interlayer insulating film which covers the multi-layered insulation body so that the recessed portion is filled;   polishing the interlayer insulating film so that an upper surface of the uppermost layer of the first stepped structure, an upper surface of the uppermost layer of the second stepped structure, and an upper surface of the interlayer insulating film are on the same plane;   selectively removing the plurality of sacrificial insulating layers to form a plurality of spaces after the polishing; and   forming conductive layers which fill the plurality of spaces to form a multi-layered structure in which the plurality of insulating layers and conductive layers are alternately stacked.   
     
     
         13 . The method of  claim 12 , wherein when etching the first region, the second region, and the area positioned between the first region and the second region,
 the first stepped structure is formed so as to have a lowermost layer that extends in a first direction towards the second stepped structure more than the uppermost layer of the first stepped structure,   the second stepped structure is formed so as to have a lowermost layer that extends in a second direction towards the first stepped structure more than the uppermost layer of the second stepped structure, and   the first direction and the second direction are opposite directions.   
     
     
         14 . The method of  claim 13 , wherein when etching the first region, the second region, and the area positioned between the first region and the second region,
 the first stepped structure is formed so as to have middle layers that extend in the first direction towards the second stepped structure more than the uppermost layer of the first stepped structure but less than the lowermost layer of the first stepped structure, and   the second stepped structure is formed so as to have middle layers that extend in the second direction towards the first stepped structure more than the uppermost layer of the second stepped structure but less than the lowermost layer of the second stepped structure.   
     
     
         15 . The method of  claim 12 , wherein the scribe region extends in a third direction that is parallel to the main surface of the semiconductor substrate and perpendicular to the first and second directions. 
     
     
         16 . The method of  claim 15 , wherein the second gate electrode extends in the third direction. 
     
     
         17 . The method of  claim 12 , wherein when removing at least an upper portion of the multi-layered insulation body formed in the scribe region,
 a first stacked structure is formed in the scribe region so as to include a plurality of insulating layers and conductive layers that are alternately stacked above the second gate electrode, and   a second stacked structure is formed in the peripheral circuit region so as to include a plurality of insulating layers and conductive layers that are alternately stacked above the first gate electrode.   
     
     
         18 . The method of  claim 17 , wherein
 the number of stacked layers in each of the first stacked structure and the second stacked structure is fewer than the number of stacked layers in either the first stepped structure or the second stepped structure.   
     
     
         19 . The method of  claim 17 , wherein the conductive layers of the first stacked structure are electrically connected to the conductive layers in the second stacked structure, respectively. 
     
     
         20 . The method of  claim 17 , wherein the conductive layers of the second stacked structure are each electrically connected to one of the conductive layers in the second stepped structure.