System, method, and apparatus for resisting hardware trojan induced leakage in combinational logics

Abstract

In one embodiment, the invention is a method and apparatus for designing combinational logics with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a design method such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several methods as shown in several embodiments. The methods include randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.

What is claimed is: 
     
         1 . A security apparatus for use in a logic circuit having at least one pair of decodable inputs and at least one pair of un-encoded outputs, comprising:
 a pair of logic inputs connected to an external data source;   a random logic state generator for randomly outputting a random logic state 1 or 0;   a first logic gate for encoding said random logic state and one of said pair of logic inputs so as to produce a pair of encoded logic outputs;   said pair of encoded logic outputs are connected to said at least one pair of decodable inputs;   a multiplexer for selecting one output of said encoded logic outputs;   a second logic gate for un-encoding said encoded logic output and said random logic state so as to produce an un-encoded output.   
     
     
         2 . The apparatus of  claim 1  wherein said first logic gate encodes according to an XOR operation. 
     
     
         3 . The apparatus of  claim 1  wherein said second logic gate encodes according to an XOR operation. 
     
     
         4 . The apparatus of  claim 1 , wherein said security apparatus is integrated with said logic circuit through quilt packaging. 
     
     
         5 . The apparatus of  claim 1 , wherein said first logic gate and said second logic gate are in direct communication with each other along said random logic state. 
     
     
         6 . The apparatus of claim I, wherein said pair of encoded logic outputs connect to said decodable inputs through at least one logic block wherein said at least one logic block contains at least one inverter. 
     
     
         7 . In a logic circuit having at least one pair of decodable inputs and at least one pair of un-encoded outputs, a security method for use therewith, comprising the steps of:
 generating a random binary logic state;   encoding said binary logic state with input data according to a first Boolean function so as to produce encoded output data;   applying said input data and said output data to said at least one pair of decodable inputs;   selecting one decodable input of said at least one pair of decodable inputs;   un-encoding said selected decodable input and said random binary logic state according to a second Boolean function so as to produce an un-encoded output.   
     
     
         8 . The method of  claim 7  wherein said first Boolean function is an XOR operation. 
     
     
         9 . The method of  claim 8  wherein said second Boolean function is an XOR operation. 
     
     
         10 . The method of  claim 7 , wherein said security method occurs within a single input/output chip. 
     
     
         11 . A secure logic chip for preventing data leakage, comprising:
 a chip having an input/output area communicating with an external area;   said external area containing logic blocks;   said input/output area including a random number generator;   wherein said random number generator outputs a random value along a random rail;   said random rail communicating with a first logic gate and a second logic gate;   wherein said first logic gate converts said random logic value and a selected single rail input signal into dual-rail representation for said external area;   said input/output area further comprising a multiplexer;   wherein said multiplexer and said second logic gate covert an external dual rail signal from said external area into a single rail output signal.   
     
     
         12 . A random rail as in  claim 11 , wherein said random rail, said first logic gate and said second logic gate are contained in their entirety within said input/output area. 
     
     
         13 . An apparatus as in  claim 12 , wherein said multiplex is housed within said input/output area. 
     
     
         14 . An apparatus as in  claim 11 , wherein said input/output area is integrated within said computer chip through quilt packaging. 
     
     
         15 . An apparatus as in  claim 11 , wherein said first logic gate and said second logic gate is an XOR gate. 
     
     
         16 . An apparatus as in  claim 11 , wherein said external area contains a first logic block and a second logic block;
 said first logic block and said second logic block communicating with said first logic gate and said multiplexer;   said first logic block having an inverter along a rail communicating with said input/output area.   
     
     
         17 . An apparatus as in  claim 16 , wherein said second logic block has at least one inverter in such a way that it is not identical to said first logic block, 
     
     
         18 . A secure logic chip for preventing data leakage, comprising:
 a chip having an input/output area communicating with an external area;   said external area containing logic blocks;   said input/output area including a random number generator;   wherein said random number generator outputs a random value along a random rail;   said random rail communicating with a first ogic gate and a second logic gate;   wherein said first logic gate encodes said random logic value and a selected single rail input signal so as to output an encoded logic value for said external area;   said input/output area further comprising a multiplexer;   wherein said multiplexer and said second XOR gate receive said encoded logic value from said external area and convert said encoded logic value into an un-encoded logic output.   
     
     
         19 . A random rail as in  claim 18 , wherein said random rail, said first logic gate and said second logic gate are contained in their entirety within said input/output area. 
     
     
         20 . An apparatus as in  claim 19 , wherein said multiplex is housed within said input/output area. 
     
     
         21 . An apparatus as in  claim 18 , wherein said input/output area is integrated within said computer chip through quilt packaging. 
     
     
         22 . An apparatus as in  claim 18 , wherein said first logic gate and said second logic gate is an XOR gate. 
     
     
         23 . An apparatus as in  claim 18 , wherein said external area contains a first logic block and a second logic block;
 said first logic block and said second logic block communicating with said first logic gate and said second logic gate;   said first logic block having an inverter along a rail communicating with said second logic gate.   
     
     
         24 . An apparatus as in  claim 23 , wherein said second logic block has at least one inverter in such a way that it is not identical to said first logic block.