Methods And Apparatus For Automated Adaptation Of Transmitter Equalizer Tap Settings

Abstract

One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to perform this method. Other embodiments, aspects, and features are also disclosed.

What is claimed is: 
     
         1 . A field-programmable gate array (FPGA) device comprising:
 a transceiver that comprises an transmit emphasis equalizer;   transmit link training circuitry comprising a transmit state machine configured to produce a transmitted (TX) link training message, wherein the training message comprises a transmitted emphasis equalizer settings update;   receive link training circuitry comprising a receive state machine configured to:
 receive a received (RX) link training message comprising a received training pattern and a received emphasis equalizer settings update; 
 update the transmit emphasis equalizer based on the received emphasis equalizer settings update; 
 calculate a bit error of the received training pattern; and 
 update a bit error counter based on the calculated bit error; and 
   adaptation circuitry configured to read the bit error counter, and determine the transmit emphasis equalizer settings update based in part on the bit error counter.   
     
     
         2 . The FPGA device of  claim 1 , wherein comprising programmable logic that comprises the transmit link training circuitry and the receive link training circuitry. 
     
     
         3 . The FPGA of  claim 1 , wherein the training message comprises a pseudo-random bit sequence. 
     
     
         4 . The FPGA device of  claim 1 , comprising a processor that comprises the adaptation circuitry. 
     
     
         5 . The FPGA device of  claim 4 , wherein the processor comprises a hard processor. 
     
     
         6 . The FPGA device of  claim 1 , comprising registers that comprise the bit error counter. 
     
     
         7 . The FPGA device of  claim 1 , wherein the transmit equalizer settings update comprises an instruction to increment, decrement, or preserve a filter coefficient of the transmit emphasis equalizer. 
     
     
         8 . The FPGA device of  claim 1 , wherein the transmit link training circuitry and the receive link training circuitry comply with an IEEE 802.3ap Backplane Ethernet standard. 
     
     
         9 . A system comprising:
 a backplane network;   a first electronic device coupled to the backplane network, comprising a first transceiver that comprises a transmit emphasis equalizer, wherein the first electronic device is configured to adjust the transmit emphasis equalizer based on a link training process; and   a second electronic device coupled to the backplane network, comprising:
 a second transceiver that comprises a second transmit emphasis equalizer; 
 a processor configured to perform instructions for adaptation, wherein the instructions for adaptation cause the processor to read a bit error counter and determine a second emphasis equalizer setting; and 
 a field programmable gate array (FPGA) device configured to perform the link training process, wherein the FPGA device is configured to:
 receive a first link training message comprising a first training pattern and first emphasis equalizer settings; 
 update the second transmit emphasis equalizer based on the first emphasis equalizer settings and the adaptive emphasis equalizer setting; 
 update the bit error counter based on errors in the first training pattern; 
 transmit a second link training message comprising a second training pattern and the second emphasis equalizer setting. 
 
   
     
     
         10 . The system of  claim 9 , wherein the first electronic device comprises an adaptation circuitry configured to determine a second emphasis equalizer setting based on a second bit error counter. 
     
     
         11 . The system of  claim 9 , wherein the backplane network comprises an IEEE 802.3ap Backplane Ethernet standard. 
     
     
         12 . The system of  claim 9 , wherein the backplane network is a 10G network compliant with Clause 72 of the IEEE 802.3 standard. 
     
     
         13 . The system of  claim 9 , wherein the first and the second link training message comprise a pseudo-random bit sequence. 
     
     
         14 . The system of  claim 9 , wherein the second electronic device comprises a processor that comprises the adaptation circuitry. 
     
     
         15 . The system of  claim 9 , comprising a registry that comprises the bit error counter. 
     
     
         16 . A method for adjusting transmitter emphasis equalizer during link training comprising:
 receiving, in a field programmable array (FPGA) of a first electronic device, and from a second electronic device, a link training message comprising a link training pattern and a first set of instructions to update a first transmitter emphasis equalizer of the electronic device;   updating the first transmitter emphasis equalizer;   storing a bit error count in a registry of the first electronic device, wherein the bit error count is based on the link training pattern;   determining a second set of instructions to update a second transmitter based on the bit error count; and   transmitting the second set of instructions to the second electronic device.   
     
     
         17 . The method of  claim 16 , wherein the determining the second set of instructions to update the second transmitter comprises performing instructions in a processor of the first electronic device, wherein the instructions comprise:
 retrieving the bit error count from the registry; and   determining a change in a coefficient of the second transmitter.   
     
     
         18 . The method of  claim 17 , wherein the coefficient comprises a main coefficient, a post coefficient, or a pre coefficient of the second transmitter. 
     
     
         19 . The method of  claim 17 , wherein the change comprises an increment or a decrement. 
     
     
         20 . The method of  claim 17 , wherein the first and the second electronic devices are coupled via a backplane network. 
     
     
         21 . A field-programmable gate array (FPGA) device comprising:
 a transceiver that comprises an transmit emphasis equalizer;   transmit link training circuitry comprising a transmit state machine configured to produce a transmitted (TX) link training message to a second electronic device, wherein the training message comprises a transmitted emphasis equalizer settings update;   receive link training circuitry comprising a receive state machine configured to:
 receive a received (RX) link training message comprising a received training pattern and a received emphasis equalizer settings update; and 
 update the transmit emphasis equalizer based on the received emphasis equalizer settings update; and 
 compare the received training pattern with a locally generated training pattern; and 
   adaptation circuitry configured to determine the transmit emphasis equalizer settings update based in part in the comparison between the received training pattern and the locally generated training pattern.   
     
     
         22 . The FPGA device of  claim 21 , wherein comparing the received training pattern and the locally generated training pattern comprises calculating a bit error rate. 
     
     
         23 . The FPGA of  claim 21 , wherein the training message comprises a pseudo-random bit sequence. 
     
     
         24 . The FPGA device of  claim 21 , wherein the transmit equalizer settings update comprises an instruction to increment, decrement, or preserve a filter coefficient of the transmit emphasis equalizer.