Circuit board and method for manufacturing the same

Abstract

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

What is claimed is: 
     
         1 . A method for manufacturing a circuit board, comprising:
 forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings;   forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer;   forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and a intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer;   forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern;   removing the patterned resist;   forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer;   a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer;   separating the carrier and the first sacrificial metal layer;   performing a first etching process to remove the first sacrificial metal layer; and   performing a second etching process to remove the first etching stop layer and the second etching stop layer.   
     
     
         2 . The method of  claim 1 , wherein the first etching stop layer and the second etching stop layer are made of the same material, and the first etching stop layer and the second etching stop layer are made of tin, titanium, aluminum, or any combination thereof. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming a metal layer on the dielectric layer when the build-up structure is formed;   wherein the second etching stop layer further covers the metal layer; and   performing a third etching process to pattern the metal layer after the second etching process is performed.   
     
     
         4 . The method of  claim 1 , further comprising:
 forming a second sacrificial metal layer on the second etching stop layer; and   removing the second sacrificial metal layer when the first sacrificial metal layer is removed.   
     
     
         5 . The method of  claim 4 , wherein a thickness of the first sacrificial metal layer is substantially the same with a thickness of the second sacrificial metal layer, and the first sacrificial metal layer and the second sacrificial metal layer are made of the same material. 
     
     
         6 . The method of  claim 1 , wherein each of the metal bumps are further divided into a first part and a second part, after the first etching stop layer and the second etching stop layer are removed, the first part is disposed in the dielectric layer, the second part protrudes from the dielectric layer, and a difference between widths of the first part and the second part is less than 4% of the width of the second part. 
     
     
         7 . The method of  claim 1 , wherein one of a plurality of the second circuit layers is formed on the dielectric layer, the others of the second circuit layers are formed in the dielectric layer, a part of the conductive vias connect the first circuit layer and the lowermost one of the second circuit layers, and the others of the conductive vias connect the second circuit layers. 
     
     
         8 . A circuit board, comprising:
 a first dielectric layer having a first surface and a second surface opposite to the first surface;   a first circuit layer buried in the first surface;   a second circuit layer disposed on the second surface;   a conductive via disposed in the first dielectric layer and connecting the first circuit layer and the second circuit layer; and   a metal bump having a first part and a second part, wherein the first part is disposed in the first dielectric layer, the second part protrudes from the first surface, and a difference between widths of the first part and the second part is less than 4% of the width of the second part.   
     
     
         9 . The circuit board of  claim 8 , further comprsing:
 a second dielectric layer disposed on a sidewall of the second part.   
     
     
         10 . The circuit board of  claim 8 , wherein an end surface of the first part and an interface between the first circuit layer and the conductive via are coplanar. 
     
     
         11 . The circuit board of  claim 8 , wherein an end surface of the first circuit layer exposed by the first surface and the first surface are coplanar. 
     
     
         12 . The circuit board of  claim 8 , wherein an edge of the first part is located outside a scope enclosed by an edge of the second part. 
     
     
         13 . The circuit board of  claim 8 , wherein an edge of the first part is located in a scope enclosed by an edge of the second part.