Adaptive Fail-Safe Power-On Control Circuit

Abstract

A circuit includes an input for receiving power from an external power supply, a voltage regulator coupled to the power input and providing regulated voltage to an external circuit and to the power supply control circuit itself, and a first switch coupled between ground and an Enable input of the voltage regulator. A control input of the first switch is coupled to the regulated voltage, such that when the voltage regulator provides regulated voltage, the first switch is closed, coupling the Enable input to ground, keeping the voltage regulator active. A first switching circuit provides manual activation and deactivation of the voltage regulator; a second switching circuit provides automatic activation of the voltage regulator whenever the power input becomes powered. An intervening circuit prevents the second switching circuit from activating the voltage regulator when the first switching circuit has deactivated it, despite the continued presence of the external power supply.

1 - 16 . (canceled) 
     
     
         17 . An audio source selection circuit for selecting between first and second audio inputs for combining with a third audio input, the selection circuit comprising:
 a first input receiving an indication that the first audio input is active;   a second input receiving an indication that the second audio input is active;   a third input receiving an indication of whether the first or second audio input is prioritized;   a fourth input receiving an indication of whether the first audio input is in a first mode or a second mode;   a first output controlling a first switch to couple the first audio input to an audio output; and   a second output controlling a second switch to couple the second audio input to an audio output.   
     
     
         18 . The selection circuit of  claim 17 , further comprising:
 a first NAND gate with its inputs connected to the first and second inputs, producing an output high unless both first and second inputs are low;   a first, normally open, transistor having a gate coupled to the fourth input, and a source coupled to ground;   a second NAND gate with both of its inputs connected to a voltage supply via a resistor, and to the drain of the first transistor through a switch that is open when the third input indicates that the first audio input is prioritized and the first transistor;   a first NOR gate with a first input connected to the output of the first NAND gate, and a second input connected to the voltage supply via the resistor;   a second NOR gate with a first input connected to the output of the first NAND gate, and a second input connected to the output of the second NAND gate;   a second, normally-open, transistor having a gate coupled to the output of the first NOR gate, a source connected to ground, and a drain connected to the first output; and   a third, normally open, transistor having a gate coupled to the output of the second NOR gate, a source connected to ground, and a drain connected to the second output;   wherein the first input is connected to the first output via a first resistor, and the second input is connected to the second output via a second resistor, such that the first input directly controls the first output, and the second input directly controls the second output, unless the corresponding NOR gates close the corresponding transistors.   
     
     
         19 . The selection circuit of  claim 17 , further comprising a prioritization circuit comprising:
 a prioritization activation circuit that determines whether the third audio input is above or below a threshold; and   a priority switch having three input states;   wherein   when the priority switch is in the first state, the prioritization circuit provides an enable output regardless of the state of the third input,   when the priority switch is in the second state, the prioritization circuit provides an enable output only when the third input is below the threshold, and   when the priority switch is in the third state, the prioritization circuit does not provide the enable output.   
     
     
         20 . The selection circuit of  claim 19 , wherein the first and second outputs comprise respective first and second AND gates, each of the first and second AND gates receiving corresponding a first or second input enable signals at its first input, and receiving the enable output from the prioritization circuit at its second input, such that the first and second AND gates only activate the respective first or second switches if the prioritization circuit provides the enable output.