Virtualizing interrupt prioritization and delivery

Abstract

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

What is claimed is: 
     
         1 . A processor comprising:
 execution circuitry to execute instructions to implement a virtualized execution environment comprising at least one Virtual Machine Monitor (VMM) and a first virtual machine control structure (VMCS), the VMM to interface virtual machines (VMs) with the processor, and the first VMCS to store a current execution state and control information associated with at least a first VM; and   interrupt management circuitry to process interrupts associated with the VMs in accordance with one or more VMCS fields including a first base address field to specify a first base address for a first memory page associated with the first VM;   the interrupt management circuitry to store priority data associated with interrupts of the first VM in the first memory page, the priority data including a processor priority value and a task priority value;   the interrupt management circuitry to set the processor priority value to the larger of the task priority value or a maximum priority value of one or more in-service interrupts; and   the interrupt management circuitry to store end of interrupt (EOI) data in the first memory page to indicate completion of a first interrupt.   
     
     
         2 . The processor of  claim 1  wherein upon the store of the EOI data, the interrupt management circuitry is to remove an indication of the first interrupt from an in-service interrupt register. 
     
     
         3 . The processor of  claim 1  wherein the processor priority value comprises data associated with a processor priority register (PPR). 
     
     
         4 . The processor of  claim 1  wherein the task priority value comprises data associated with a task priority register (TPR). 
     
     
         5 . The processor of  claim 1  wherein the EOI data comprises data associated with an end of interrupt (EOI) register. 
     
     
         6 . A method comprising:
 storing, in a virtual machine control structure (VMCS), a current execution state and control information associated with a virtual machine (VM) interfaced with a processor by a virtual machine monitor (WM) in a virtualized execution environment;   processing interrupts associated with the VM in accordance with one or more VMCS fields including a base address field to specify a base address for a memory page associated with the VM;   storing priority data associated with interrupts of the VM in the memory page, the priority data including a processor priority value and a task priority value;   setting the processor priority value to the larger of the task priority value or a maximum priority value of one or more in-service interrupts; and   storing end of interrupt (EOI) data in the memory page to indicate completion of a first interrupt.   
     
     
         7 . The method of  claim 6  further comprising removing an indication of the first interrupt form an in-service interrupt register responsive to storing the EOI data. 
     
     
         8 . The method of  claim 6  wherein the processor priority value comprises data associated with a processor priority register (PPR). 
     
     
         9 . The method of  claim 6  wherein the task priority value comprises data associated with a task priority register (TPR). 
     
     
         10 . The method of  claim 6  wherein the EOI data comprises data associated with an end of interrupt (EOI) register. 
     
     
         11 . A non-transitory machine-readable medium storing instructions which when executed by a processor cause the processor to perform a method, the method comprising:
 storing, in a virtual machine control structure (VMCS), a current execution state and control information associated with a virtual machine (VM) interfaced with a processor by a virtual machine monitor (WM) in a virtualized execution environment;   processing interrupts associated with the VM in accordance with one or more VMCS fields including a base address field to specify a base address for a memory page associated with the VM;   storing priority data associated with interrupts of the VM in the memory page, the priority data including a processor priority value and a task priority value;   setting the processor priority value to the larger of the task priority value or a maximum priority value of one or more in-service interrupts; and   storing end of interrupt (EOI) data in the memory page to indicate completion of a first interrupt.   
     
     
         12 . The non-transitory machine-readable medium of  claim 11 , wherein the method further comprises removing an indication of the first interrupt form an in-service interrupt register responsive to storing the EOI data. 
     
     
         13 . The non-transitory machine-readable medium of  claim 11 , wherein the processor priority value comprises data associated with a processor priority register (PPR). 
     
     
         14 . The non-transitory machine-readable medium of  claim 11 , wherein the task priority value comprises data associated with a task priority register (TPR). 
     
     
         15 . The non-transitory machine-readable medium of  claim 11 , wherein the EOI data comprises data associated with an end of interrupt (EOI) register.