Providing State Storage in a Processor for System Management Mode

Abstract

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of cores formed on a single semiconductor die;   decode circuitry of at least one core to decode instructions of one or more threads;   execution circuitry of the at least one core to perform out-of-order execution of the instructions of the one or more threads;   the execution circuitry to execute system management mode (SMM) handler code from a designated system memory address region to perform system management operations in response to a system management interrupt (SMI);   save/restore circuitry to save at least a portion of a first execution state of a first thread to a cache prior to entering the SMM; and   the execution circuitry to execute a resume instruction included in the SMM handler code to cause the save/restore circuitry to restore the at least a portion of the first execution state from the cache upon exiting the SMM;   wherein the processor does not invalidate the cache responsive to entering or existing the   
     
     
         2 . The processor of  claim 1  wherein the portion of the first execution state of the first thread is to be saved in cache lines which map to a system management random access memory (SMRAM) address region. 
     
     
         3 . The processor of  claim 1  wherein the designated system memory address region maps to a system management random access memory (SMRAM). 
     
     
         4 . The processor of  claim 1  further comprising:
 fetch circuitry to fetch the instructions of the one or more threads. 
 
     
     
         5 . The processor of  claim 1  further comprising:
 an integrated memory controller to couple the plurality of cores to a system memory. 
 
     
     
         6 . The processor of  claim 1  further comprising:
 a last level cache (LLC) shared by the plurality of cores. 
 
     
     
         7 . A method comprising:
 executing, in execution circuitry of a processor, system management mode (SMM) handler code from a designated system memory address region to perform system management operations in response to a system management interrupt (SMI), the processor including a plurality of cores formed on a single semiconductor die;   saving, by save/restore circuitry, of the processor, at least a portion of a first execution state of a first thread to a cache of the processor prior to entering the SMM; and   executing, in the execution circuitry, a resume instruction included in the SMM handler code to cause the save/restore circuitry to restore the at least a portion of the first execution state from the cache upon exiting the SMM, and not invalidating the cache responsive to entering or exiting the SMM.   
     
     
         8 . The method of  claim 7  further comprising saving the portion of the first execution state of the first thread in cache lines which map to a system management random access memory (SRAM) address region. 
     
     
         9 . The method of  claim 7  wherein the designated system memory address region maps to a system management random access memory (SMRAM). 
     
     
         10 . The method of  claim 7  further comprising fetching, via fetch circuitry of the processor, instructions of one or more threads. 
     
     
         11 . The method of  claim 7  further comprising coupling, via an integrated memory controller of the processor, the plurality of cores to a system memory. 
     
     
         12 . The method of  claim 7  further comprising sharing a last level cache (LLC) of the processor by the plurality of cores. 
     
     
         13 . At least one computer readable storage medium comprising instructions that when executed enable a system to:
 execute, in execution circuitry of a processor, system management mode (SMM) handler code from a designated system memory address region to perform system management operations in response to a system management interrupt (SMI), the processor including a plurality of cores formed on a single semiconductor die;   save, by save/restore circuitry, of the processor, at least a portion of a first execution state of a first thread to a cache of the processor prior to entry into the SMM; and   execute, in the execution circuitry, a resume instruction included in the SMM handler code to cause the save/restore circuitry to restore the at least a portion of the first execution state from the cache upon exit the SMM, and wherein the cache is not invalidated responsive to entry into or exit from the SMM.   
     
     
         14 . The at least one computer readable storage medium of  claim 13  further comprising instructions that when executed enable the system to save the portion of the first execution state of the first thread in cache lines which map to a system management random access memory (SRAM) address region. 
     
     
         15 . The at least one computer readable storage medium of  claim 13  wherein the designated system memory address region is to map to a system management random access memory (SMRAM). 
     
     
         16 . The at least one computer readable storage medium of  claim 13  further comprising instructions that when executed enable the system to fetch, via fetch circuitry of the processor, instructions of one or more threads.