S-Contact for SOI

Abstract

Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

1 . A device comprising:
 a semiconductor substrate having a high resistivity, the high resistivity being based on a nominal doping of the semiconductor substrate;   a trap rich layer overlying the semiconductor substrate   an insulation layer overlying the trap rich layer;   an active layer overlying the insulation layer and comprising active regions and isolation regions of the device;   a transistor formed in an isolated portion of the active layer, the transistor comprising a drain region, a source region and a gate channel region; and   a first conductive structure resistively connecting one of: a) a drain contact or a source contact, and b) a gate contact to the semiconductor substrate, the first conductive structure comprising:
 a first conductive line connecting the one of a) and b) to a first conductive contact, the first conductive contact extending through the active layer at a region of the active layer outside the isolated portion of the active layer, further extending through the insulation layer and penetrating the trap rich layer to make resistive contact with the semiconductor substrate at a region of the semiconductor substrate that is doped at the nominal doping only. 
   
     
     
         2 . The device of  claim 1 , wherein the first conductive contact extends through the active layer at an isolation region of the device. 
     
     
         3 . The device of  claim 1 , wherein the first conductive contact extends through the active layer at an active region of the device. 
     
     
         4 . The device of  claim 1 , wherein the first conductive contact extends through the trap rich layer to make direct contact with semiconductor substrate at the region of the semiconductor substrate that is doped at the nominal doping only. 
     
     
         5 . The device of  claim 1 , wherein the first conductive contact penetrates the trap rich layer at a depth corresponding to a desired resistance value of the resistive contact. 
     
     
         6 . The device of  claim 1 , wherein a resistivity value of the semiconductor substrate is in a range of 3,000 to 20,000 ohm-cm. 
     
     
         7 . The device of  claim 1 , wherein a resistivity value of the semiconductor substrate is greater than 3,000 ohm-cm. 
     
     
         8 . A method for providing a discharge path to a silicon-on-insulator (SOI) transistor device, the method comprising:
 (i) forming an active layer on a semiconductor substrate having a high resistivity, the active layer being isolated from the semiconductor substrate via an insulation layer overlying the semiconductor substrate, the high resistivity being based on a nominal doping of the semiconductor substrate;   (ii) forming active regions of the transistor device within an isolated portion of the active layer, the active regions comprising a source region, a drain region and a gate channel region of the transistor device;   (iii) forming a first conductive structure resistively connecting at least one of: a) a drain contact or a source contact, and b) a gate contact of the transistor device to the semiconductor substrate, the first conducting structure being formed by:
 forming a first conductive line connecting the at least one of a) and b) to a first conductive contact; 
 extending the first conductive contact through the active layer at a region of the active layer outside the isolated portion of the active layer, and through the insulation layer to make a resistive contact with the semiconductor substrate at a region of the semiconductor substrate that is doped at the nominal doping only, and 
   (iv) based on the forming of the first conductive structure, providing a first discharge path to the transistor device.   
     
     
         9 . The method of  claim 8 , wherein the first conductive contact extends through an isolation region of the active layer and makes contact with the semiconductor substrate at the region of the semiconductor substrate that is doped at the nominal doping only. 
     
     
         10 . The method of  claim 9 , wherein the isolation region is a shallow trench isolation (STI) region. 
     
     
         11 . The method of  claim 8 , wherein the first conductive contact extends through the active layer at an active region of a separate semiconductor device formed within the active layer and makes contact with the semiconductor substrate at the region of the semiconductor substrate that is doped at the nominal doping only. 
     
     
         12 . The method of  claim 8 , further comprising:
 forming a second conductive structure; and   based on the forming, resistively connecting the other of the at least one of a) and b) to the semiconductor substrate at another region of the semiconductor substrate that is doped at the nominal doping only.   
     
     
         13 . The method of  claim 12 , wherein the forming of the second conductive structure comprises:
 forming a second conductive line connecting the other of the one of a) and b) to a second conductive contact;   extending the second conductive contact through the active layer at a region of the active layer outside the isolated portion of the active layer, and through the insulation layer to make a resistive contact with the semiconductor substrate, and   based on the forming of the first conductive structure, providing a second discharge path to the transistor device.   
     
     
         14 . The method of  claim 8 , wherein a resistivity value of the semiconductor substrate is in a range of 3,000 to 20,000 ohm-cm. 
     
     
         15 . The method of  claim 8 , wherein a resistivity value of the semiconductor substrate is greater than 3,000 ohm-cm. 
     
     
         16 . The method of  claim 8 , wherein the first conductive line penetrates a trap rich layer formed between the semiconductor substrate and the insulation layer. 
     
     
         17 . The method of  claim 16 , wherein the first conductive line extends through the trap rich layer to make contact with the semiconductor substrate at the region of the semiconductor substrate that is doped at the nominal doping only. 
     
     
         18 . The method of  claim 8 , wherein a resistance between the first conductive contact and the semiconductor substrate is in a range of 0.2 to 20 G-ohm. 
     
     
         19 . The device of  claim 1 , wherein a resistance between the first conductive contact and the semiconductor substrate is in a range of 0.2 to 20 G-ohm.