Interface virtualization and fast path for network on chip

Abstract

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

What is claimed is: 
     
         1 . A Network on Chip (NoC), comprising:
 a plurality of channels;   at least one receiving hardware element; and   at least one transmitting hardware element configured to:
 transmit a valid signal to the at least one receiving hardware element on a channel of the plurality of channels, and 
 transmit a virtual channel (VC) valid signal as a virtual channel indicator for a virtual channel of a plurality of virtual channels designated for transmission of data and transmit the data on the virtual channel designated for the transmission of the data; 
 wherein the at least one receiving hardware element is configured to transmit a VC credit to the at least one transmitting hardware element. 
   
     
     
         2 . The NoC of  claim 1 , wherein the at least one transmitting hardware element is configured to not transmit the data packet on the virtual channel until a VC credit is obtained. 
     
     
         3 . The NoC of  claim 1 , wherein the plurality of channels comprises one or more VCs, each of the plurality of channels being configurable to be independently controlled for mapping to an interface virtual VCs. 
     
     
         4 . The NoC of  claim 1 , further comprising a virtual interface connected to the NoC for virtual channels to interact with agents of a System on Chip (SoC). 
     
     
         5 . The NoC of  claim 4 , wherein the virtual interface comprises a read channel. 
     
     
         6 . The NoC of  claim 1 , wherein the at least one transmitting element is further configured to:
 manage VC credits received from one or more of the at least one receiving hardware element; and   conduct arbitration based on whether a message destination is associated with a VC credit from the managed VC credits.   
     
     
         7 . The NoC of  claim 1 , wherein the at least one transmitting hardware element is configured to:
 arbitrate messages for transmitting through prioritizing messages that are associated with a VC credit.   
     
     
         8 . The NoC of  claim 1 , wherein the at least one receiving hardware element is configured to:
 provide a reservation for a VC to one or more of the at least one transmitting hardware element based on at least one of management of dedicated VC credits to the one or more of the at least one transmitting hardware element, and an inference of priority from the one or more of the at least one transmitting hardware element.   
     
     
         9 . The NoC of  claim 1 , wherein the at least one receiving hardware element is a NoC element and the at least one transmitting hardware element is an agent of the System on Chip (SoC). 
     
     
         10 . A hardware interconnect system, comprising:
 a plurality of channels;   at least one receiving hardware element; and   at least one transmitting hardware element configured to:
 transmit a valid signal to the at least one receiving hardware element on a channel of the plurality of channels, and 
 transmit a virtual channel (VC) valid signal as a virtual channel indicator for a virtual channel of a plurality of virtual channels designated for transmission of data and transmit the data on the virtual channel designated for the transmission of the data; 
 wherein the at least one receiving hardware element is configured to transmit a VC credit to the at least one transmitting hardware element. 
   
     
     
         11 . The hardware interconnect system of  claim 10 , wherein the at least one transmitting hardware element is configured to not transmit the data packet on the virtual channel until a VC credit is obtained. 
     
     
         12 . The hardware interconnect system of  claim 10 , wherein the plurality of channels comprises one or more VCs, each of the plurality of channels being configurable to be independently controlled for mapping to an interface virtual VCs. 
     
     
         13 . The hardware interconnect system of  claim 10 , further comprising a virtual interface for virtual channels to map to physical channels of the hardware interconnect system. 
     
     
         14 . The hardware interconnect system of  claim 13 , wherein the virtual interface comprises a read channel. 
     
     
         15 . The hardware interconnect system of  claim 10 , wherein the at least one transmitting element is further configured to:
 manage VC credits received from one or more of the at least one receiving hardware element; and   conduct arbitration based on whether a message destination is associated with a VC credit from the managed VC credits.   
     
     
         16 . The hardware interconnect system of  claim 10 , wherein the at least one transmitting hardware element is configured to:
 arbitrate messages for transmitting through prioritizing messages that are associated with a VC credit.   
     
     
         17 . The hardware interconnect system of  claim 10 , wherein the at least one receiving hardware element is configured to:
 provide a reservation for a VC to one or more of the at least one transmitting hardware element based on at least one of management of dedicated VC credits to the one or more of the at least one transmitting hardware element, and an inference of priority from the one or mote of the at least one transmitting hardware element.   
     
     
         18 . The hardware interconnect system of  claim 10 , wherein the at least one receiving hardware element is a NoC element and the at least one transmitting hardware element is an agent of the System on Chip (SoC).