Header replication in accelerated tcp (transport control protocol) stack processing

Abstract

In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a processor;   a port to receive a packet comprising a header of a particular protocol and a payload; and   programmable logic to:
 receive the packet, and 
 split the packet to cause the header to be pushed into a first portion of computer memory and the payload to be pushed directly into a second, different portion of the computer memory; 
   wherein the first portion of the computer memory comprises a cache of the processor.   
     
     
         2 . The apparatus of  claim 1 , further comprising the computer memory. 
     
     
         3 . The apparatus of  claim 2 , wherein the computer memory comprises off-chip memory. 
     
     
         4 . The apparatus of  claim 1 , further comprising a graphic processing unit (GPU). 
     
     
         5 . The apparatus of  claim 1 , further comprising a coprocessor. 
     
     
         6 . The apparatus of  claim 1 , further comprising a network interface controller (NIC). 
     
     
         7 . The apparatus of  claim 1 , wherein the payload is pushed directly to the second portion of the computer memory via a direct memory access. 
     
     
         8 . The apparatus of  claim 1 , wherein the second portion of the computer memory comprises system memory. 
     
     
         9 . The apparatus of  claim 1 , wherein the particular protocol comprises an Ethernet-based protocol. 
     
     
         10 . The apparatus of  claim 1 , wherein the packet comprises a Transmission Control Protocol/Internet Protocol (TCP/IP) packet. 
     
     
         11 . The apparatus of  claim 10 , wherein the header comprises a TCP/IP header. 
     
     
         12 . A method, comprising:
 receiving a packet comprising a header of a particular protocol and a payload; and   splitting the packet to cause the header to be pushed into a first portion of a memory and the payload to be pushed directly into a second, different portion of the memory;   wherein the first portion of the memory comprises a processor cache.   
     
     
         13 . The method of  claim 12 , wherein the payload is pushed directly to the second portion of the memory via a direct memory access. 
     
     
         14 . The method of  claim 12 , wherein the second portion of the memory comprises system memory. 
     
     
         15 . The method of  claim 12 , wherein the particular protocol comprises an Ethernet-based protocol. 
     
     
         16 . The method of  claim 12 , wherein the packet comprises a Transmission Control Protocol/Internet Protocol (TCP/IP) packet. 
     
     
         17 . The method of  claim 16 , wherein the header comprises a TCP/IP header. 
     
     
         18 . A system, comprising:
 an integrated circuit, comprising:
 a processor; 
 a port to receive a packet comprising a header of a particular protocol and a payload; and 
   programmable logic to:
 receive the packet, and 
 split the packet to cause the header to be pushed into a first portion of a memory and the payload to be pushed directly into a second, different portion of the memory, wherein the first portion of the memory comprises a cache of the processor; and 
   at least one other component coupled to the processor.   
     
     
         19 . The system of  claim 18 , wherein the other component comprises a graphics processing unit. 
     
     
         20 . The system of  claim 18 , further comprising off-chip memory. 
     
     
         21 . A system, comprising:
 means for receiving a packet comprising a header of a particular protocol and a payload; and   means for splitting the packet to cause the header to be pushed into a first portion of computer memory and the payload to be pushed directly into a second, different portion of the computer memory;   wherein the first portion of the computer memory comprises a cache of a processor.