Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Abstract

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

What is claimed is: 
     
         1 . A method for fabricating a photodetector and a transistor on a same semiconductor substrate, the method comprising:
 forming, on a semiconductor substrate, a structure having two mesas, one mesa for the transistor and one mesa for the photodetector, wherein a mesa groove between the two mesas forms an isolation trench, and wherein the two mesas are of a same height;   adjusting a relative height between the mesa for the photodetector and the mesa for the transistor; and   forming the transistor and the photodetector on respective mesas.   
     
     
         2 . The method of  claim 1 , wherein said adjusting the relative height comprises:
 reducing a height of the mesa for the photodetector until a top surface of the mesa for the photodetector is lower than a top surface of the mesa for the transistor but higher than a bottom surface of the isolation trench.   
     
     
         3 . The method of  claim 2 , wherein said reducing the height of the mesa for the photodetector comprises:
 depositing a protection layer over the mesa for the transistor for protection against etching; and   etching the semiconductor substrate to remove substrate material in the mesa for the photodetector to reduce the height of the mesa for the photodetector.   
     
     
         4 . The method of  claim 1 , wherein said adjusting the relative height comprises:
 increasing a height of the mesa for the transistor by epitaxial growth.   
     
     
         5 . The method of  claim 1 , wherein said forming the structure having two mesas comprises:
 depositing a stopping layer, with patterns defining the two mesas, over the semiconductor substrate; and   etching the semiconductor substrate to create the structure having the two mesas.   
     
     
         6 . The method of  claim 1 , further comprising:
 depositing isolation oxide in the mesa groove to form the isolation trench.   
     
     
         7 . The method of  claim 6 , wherein the isolation dielectric material comprises silicon oxide or silicon nitride or a combination thereof. 
     
     
         8 . The method of  claim 1 , further comprising:
 forming, on the semiconductor substrate, dummy fill shapes of at least two sizes at suitable locations for uniform process loading across a wafer during a subsequent epitaxial growth or a subsequent material removal process, wherein one size of the dummy fill shape dedicated for the transistor, and wherein another size of the dummy fill shape dedicated for the photodetector.   
     
     
         9 . The method of  claim 8 , wherein the subsequent material removal process includes at least one of: a chemical mechanical polishing process, or a reactive ion etching process. 
     
     
         10 . The method of  claim 1 , wherein the photodetector contains germanium for light absorption, and wherein the transistor is a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). 
     
     
         11 . The method of  claim 1 , wherein the photodetector is a normal incidence type that can receive incident light from the top or the bottom of the photodetector. 
     
     
         12 . A device comprising:
 a semiconductor substrate including a first surface, a second surface, and a third surface;   a semiconductor transistor formed on the second surface higher than the first surface; and   a semiconductor photodetector formed on the third surface higher than the first surface but lower than the second surface, wherein the first surface, being lower than both the second and the third surfaces, forms an isolation trench between the semiconductor photodetector and semiconductor transistor.   
     
     
         13 . The device of  claim 12 , wherein a resulting height of the semiconductor photodetector is lower than a bottom surface of a lowest layer of metal interconnects for the semiconductor transistor. 
     
     
         14 . The device of  claim 12 , wherein the semiconductor photodetector is formed at a different horizontal location on said semiconductor substrate than the semiconductor transistor. 
     
     
         15 . The device of  claim 12 , wherein the semiconductor photodetector and the semiconductor transistor are formed on two separate mesas, one mesa for the transistor and one mesa for the photodetector, and wherein a mesa groove between the two mesas forms an isolation trench. 
     
     
         16 . The device of  claim 15 , wherein the isolation trench is filled by at least one or more of: oxide-based dielectric materials, or nitride-based dielectric materials. 
     
     
         17 . The device of  claim 12 , wherein the photodetector includes a p-type semiconductor region, an n-type semiconductor region, and a photosensitive semiconductor region. 
     
     
         18 . The device of  claim 17 , wherein an n-type surface of the photodetector is located at an interface between the photodetector and the substrate. 
     
     
         19 . The device of  claim 17 , wherein the photosensitive semiconductor region comprises a stack of semiconductor materials including substrate semiconductor material with a first dielectric constant and a photosensitive material with a second dielectric constant, the second dielectric constant higher than the first dielectric constant. 
     
     
         20 . The device of  claim 19 , wherein a thickness ratio between the substrate semiconductor material and other semiconductor materials in the photosensitive semiconductor region combined is greater than 1 to 5. 
     
     
         21 . The device of  claim 12 , further comprising:
 a select number of dummy fill shapes about a size of the transistor, wherein the dummy fill shapes of the size of the transistor are formed on a surface that is at a same height as the second surface.   
     
     
         22 . The device of  claim 12 , further comprising:
 a select number of dummy fill shapes about a size of the photodetector, wherein the dummy fill shapes of the size of the photodetector are formed on a surface that is at the same height as the third surface.   
     
     
         23 . The device of  claim 12 , wherein the photodetector contains germanium for light absorption, and wherein the transistor is a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). 
     
     
         24 . The device of  claim 12 , wherein the photodetector includes a mirror structure for reducing a thickness of a light absorption region of the photodetector.