Nanowire arrays for neurotechnology and other applications

Abstract

The present invention generally relates to nanowires. In one aspect, the present invention is generally directed to systems and methods of individually addressing nanowires on a surface, e.g., that are substantially upstanding or vertically-oriented with respect to the surface. In some cases, one or more nanowires may be individually addressed using various integrated circuit (“IC”) technologies, such as CMOS. For example, the nanowires may form an array on top of an active CMOs integrated circuit.

What is claimed is: 
     
         1 . An article, comprising:
 a plurality of upstanding nanowires on a substrate, in electrical communication with an integrated circuit.   
     
     
         2 . The article of  claim 1 , wherein the substrate is physically connected to the integrated circuit. 
     
     
         3 . The article of any one of  claims 1 - 2 , wherein the substrate is substantially planar. 
     
     
         4 . The article of any one of  claims 1 - 3 , wherein the integrated circuit is substantially planar. 
     
     
         5 . The article of any one of  claims 1 - 4 , wherein the substrate is adjacent the integrated circuit. 
     
     
         6 . The article of any one of  claims 1 - 5 , wherein the integrated circuit comprises a CMOS. 
     
     
         7 . The article of any one of  claims 1 - 6 , wherein at least some of the nanowires are individually addressable via the integrated circuit. 
     
     
         8 . The article of any one of  claims 1 - 7 , wherein each of the nanowires are individually addressable via the integrated circuit. 
     
     
         9 . The article of any one of  claims 1 - 8 , wherein the nanowires are attached to the substrate along a substantially vertical direction relative to the substrate. 
     
     
         10 . The article of any one of  claims 1 - 9 , wherein at least some of the nanowires are silicon oxide nanowires. 
     
     
         11 . The article of any one of  claims 1 - 10 , wherein the integrated circuit comprises a plurality of connection sites in electrical communication with one or more nanowires of the plurality of nanowires. 
     
     
         12 . The article of  claim 11 , wherein at least a portion of the connection sites comprise an amplifier unit and/or a stimulator unit. 
     
     
         13 . The article of  claim 12 , wherein at least a portion of the amplifier units comprise a high-pass filter comprising a plurality of diodes. 
     
     
         14 . The article of any one of  claims 11 - 13 , wherein the integrated circuit comprises at least about 1,000 connection sites. 
     
     
         15 . The article of any one of  claims 12 - 14 , wherein the integrated circuit comprises at least about 1,000 amplifier units and/or at least about 1,000 stimulator units. 
     
     
         16 . The article of any one of  claims 1 - 15 , wherein the plurality of upstanding nanowires comprises at least about 1,000 nanowires. 
     
     
         17 . The article of any one of  claims 1 - 16 , wherein the average length of the nanowires is 0.1-10 micrometers (μm). 
     
     
         18 . The article of any one of  claims 1 - 17 , wherein the average diameter of the nanowires is 50-300 nm. 
     
     
         19 . The article of any one of  claims 1 - 18 , wherein the density of the nanowires is 0.05-5 nanowires per micrometer 2  (μm 2 ). 
     
     
         20 . The article of any one of  claims 1 - 19 , further comprising a cell in electrical communication with one or more nanowires of the plurality of nanowires. 
     
     
         21 . The article of any one of  claims 1 - 20 , further comprising a cell penetrated by one or more nanowires of the plurality of nanowires. 
     
     
         22 . The article of  claim 21 , wherein the cell is a neuron or a cardiomyocyte. 
     
     
         23 . The article of any one of  claims 1 - 22 , wherein the substrate is a silicon substrate. 
     
     
         24 . The article of any one of  claims 1 - 23 , wherein the upstanding nanowires form an angle with respect to the substrate, on average, of between about 80° and about 100°. 
     
     
         25 . A method, comprising:
 inserting one or more nanowires into a cell, wherein the one or more nanowires are upstanding nanowires on a substrate and are in electrical communication with an integrated circuit.   
     
     
         26 . The method of  claim 25 , further comprising recording an electrical signal from the cell through at least one of the nanowires. 
     
     
         27 . The method of any one of  claims 25 - 26 , further comprising applying an electrical stimulus to the cell through at least one of the nanowires. 
     
     
         28 . The method of any one of  claims 25 - 27 , wherein the substrate is physically connected to the integrated circuit. 
     
     
         29 . The method of any one of  claims 25 - 28 , wherein the substrate is substantially planar. 
     
     
         30 . The method of any one of  claims 25 - 29 , wherein the integrated circuit is substantially planar. 
     
     
         31 . The method of any one of  claims 25 - 30 , wherein the substrate is adjacent the integrated circuit. 
     
     
         32 . The method of any one of  claims 25 - 31 , wherein the integrated circuit comprises a CMOS. 
     
     
         33 . The method of any one of  claims 25 - 32 , wherein at least some of the nanowires are individually addressable via the integrated circuit. 
     
     
         34 . The method of any one of  claims 25 - 33 , wherein each of the nanowires are individually addressable via the integrated circuit. 
     
     
         35 . The method of any one of  claims 25 - 34 , wherein the nanowires are attached to the substrate along a substantially vertical direction relative to the substrate. 
     
     
         36 . The method of any one of  claims 25 - 35 , wherein at least some of the nanowires are silicon oxide nanowires. 
     
     
         37 . The method of any one of  claims 25 - 36 , wherein the integrated circuit comprises a plurality of connection sites in electrical communication with one or more of the nanowires. 
     
     
         38 . The method of  claim 37 , wherein at least a portion of the connection sites comprise an amplifier unit and/or a stimulator unit. 
     
     
         39 . The method of  claim 38 , further comprising recording an electrical signal from the cell through an amplifier unit. 
     
     
         40 . The method of any one of  claims 38 - 39 , further comprising applying an electrical stimulus to the cell through a stimulator unit. 
     
     
         41 . The method of any one of  claims 25 - 40 , wherein the average length of the nanowires is 0.1-10 micrometers (μm). 
     
     
         42 . The method of any one of  claims 25 - 41 , wherein the average diameter of the nanowires is 50-300 nm. 
     
     
         43 . The method of any one of  claims 25 - 42 , wherein the density of the nanowires is 0.05-5 nanowires per micrometer 2  (μm 2 ). 
     
     
         44 . The method of any one of  claims 25 - 43 , wherein the cell is in electrical communication with at least one of the nanowires. 
     
     
         45 . The method of any one of  claims 25 - 44 , wherein the cell is a neuron or a cardiomyocyte. 
     
     
         46 . The method of any one of  claims 25 - 45 , wherein the substrate is a silicon substrate. 
     
     
         47 . The method of any one of  claims 25 - 46 , wherein the upstanding nanowires form an angle with respect to the substrate, on average, of between about 80° and about 100°. 
     
     
         48 . A method, comprising:
 applying electroporation and/or voltage to a cell using one or more nanowires inserted into a cell, wherein the one or more nanowires are upstanding nanowires on a substrate and are in electrical communication with an integrated circuit.   
     
     
         49 . The method of  claim 48 , further comprising recording one or more electrical signals from the cell through at least one of the nanowires. 
     
     
         50 . The method of any one of  claims 48 - 49 , wherein the substrate is physically connected to the integrated circuit. 
     
     
         51 . The method of any one of  claims 48 - 50 , wherein the substrate is substantially planar. 
     
     
         52 . The method of any one of  claims 48 - 51 , wherein the integrated circuit is substantially planar. 
     
     
         53 . The method of any one of  claims 48 - 52 , wherein the substrate is adjacent the integrated circuit. 
     
     
         54 . The method of any one of  claims 48 - 53 , wherein the integrated circuit comprises a CMOS. 
     
     
         55 . The method of any one of  claims 48 - 54 , wherein at least some of the nanowires are individually addressable via the integrated circuit. 
     
     
         56 . The method of any one of  claims 48 - 55 , wherein each of the nanowires are individually addressable via the integrated circuit. 
     
     
         57 . The method of any one of  claims 48 - 56 , wherein the nanowires are attached to the substrate along a substantially vertical direction relative to the substrate. 
     
     
         58 . The method of any one of  claims 48 - 57 , wherein at least some of the nanowires are silicon oxide nanowires. 
     
     
         59 . The method of any one of  claims 48 - 58 , wherein the average length of the nanowires is 0.1-10 micrometers (μm). 
     
     
         60 . The method of any one of  claims 48 - 59 , wherein the average diameter of the nanowires is 50-300 nm. 
     
     
         61 . The method of any one of  claims 48 - 60 , wherein the density of the nanowires is 0.05-5 nanowires per micrometer 2  (μm 2 ). 
     
     
         62 . The method of any one of  claims 48 - 61 , wherein the cell is in electrical communication with at least one of the one or more nanowires. 
     
     
         63 . The method of any one of  claims 48 - 62 , wherein the cell is a neuron or a cardiomyocyte. 
     
     
         64 . The method of any one of  claims 48 - 63 , wherein the substrate is a silicon substrate. 
     
     
         65 . The method of any one of  claims 48 - 64 , wherein the upstanding nanowires form an angle with respect to the substrate, on average, of between about 80° and about 100°. 
     
     
         66 . A method, comprising:
 exposing a plurality of cells to one or more compounds, wherein at least some of the cells are penetrated with one or more nanowires, wherein the one or more nanowires are upstanding nanowires on a substrate and are in electrical communication with an integrated circuit.   
     
     
         67 . The method of  claim 66 , further comprising recording one or more electrical signals from at least a portion of the cells through at least a portion of the nanowires. 
     
     
         68 . The method of any one of  claims 66 - 67 , further comprising applying an electrical stimulus to at least a portion of the cells through at least a portion of the nanowires. 
     
     
         69 . The method of any one of  claims 66 - 68 , wherein the substrate is physically connected to the integrated circuit. 
     
     
         70 . The method of any one of  claims 66 - 69 , wherein the substrate is substantially planar. 
     
     
         71 . The method of any one of  claims 66 - 70 , wherein the integrated circuit is substantially planar. 
     
     
         72 . The method of any one of  claims 66 - 71 , wherein the substrate is adjacent the integrated circuit. 
     
     
         73 . The method of any one of  claims 66 - 72 , wherein the integrated circuit comprises a CMOS. 
     
     
         74 . The method of any one of  claims 66 - 73 , wherein at least some of the nanowires are individually addressable via the integrated circuit. 
     
     
         75 . The method of any one of  claims 66 - 74 , wherein each of the nanowires are individually addressable via the integrated circuit. 
     
     
         76 . The method of any one of  claims 66 - 75 , wherein the nanowires are attached to the substrate along a substantially vertical direction relative to the substrate. 
     
     
         77 . The method of any one of  claims 66 - 76 , wherein at least some of the nanowires are silicon oxide nanowires. 
     
     
         78 . The method of any one of  claims 66 - 77 , wherein the average length of the nanowires is 0.1-10 micrometers (μm). 
     
     
         79 . The method of any one of  claims 66 - 78 , wherein the average diameter of the nanowires is 50-300 nm. 
     
     
         80 . The method of any one of  claims 66 - 79 , wherein the density of the nanowires is 0.05-5 nanowires per micrometer 2  (μm 2 ). 
     
     
         81 . The method of any one of  claims 66 - 80 , wherein at least some of the cells are in electrical communication at least one of the nanowires. 
     
     
         82 . The method of any one of  claims 66 - 81 , wherein the cell is a neuron or a cardiomyocyte. 
     
     
         83 . The method of any one of  claims 66 - 82 , wherein the substrate is a silicon substrate. 
     
     
         84 . The method of any one of  claims 66 - 83 , wherein the upstanding nanowires form an angle with respect to the substrate, on average, of between about 80° and about 100°. 
     
     
         85 . The method of any one of  claims 66 - 84 , wherein the one or more compounds includes one or more drug candidates suspected of interacting with at least some of the cells. 
     
     
         86 . The method of any one of  claims 66 - 85 , wherein the one or more compounds include one or more drug candidates suspected of affecting an ion channel. 
     
     
         87 . The method of any one of  claims 66 - 86 , wherein the one or more compounds include one or more drug candidates suspected of affecting a neuronal nicotinic acetylcholine receptor. 
     
     
         88 . A method of fabricating a device, comprising:
 depositing a nanowire-material-comprising layer on an integrated circuit;   generating an etch mask;   etching the nanowire-material-comprising layer to form one or more nanowires; and   depositing a conformal coating comprising an electrically conductive material on the one or more nanowires.   
     
     
         89 . The method of  claim 88 , wherein the nanowire-material-comprising layer comprises SiO 2 . 
     
     
         90 . The method of any one of  claims 88 - 89 , further comprising depositing a protective layer on an integrated circuit prior to the step of depositing the nanowire-material-comprising layer on the integrated circuit. 
     
     
         91 . The method of  claim 90 , wherein the protective layer comprises Pt and/or Ti. 
     
     
         92 . The method of any one of  claims 88 - 91 , further comprising depositing a passivation layer on the one or more nanowires coated with an electrically conductive material. 
     
     
         93 . The method of  claim 92 , wherein the passivation layer comprises SiO 2  and/or Al 2 O 3 . 
     
     
         94 . The method of any one of  claims 92 - 93 , further comprising etching the tips of the one or more nanowires to remove the passivation layer and expose the electrically conductive material. 
     
     
         95 . The method of any one of  claims 88 - 94 , wherein the electrically conductive material comprises a metal.