US2018175803A1PendingUtilityA1

Radio frequency integrated circuit (rfic) charged-device model (cdm) protection

Assignee: QUALCOMM INCPriority: Mar 15, 2013Filed: Feb 14, 2018Published: Jun 21, 2018
Est. expiryMar 15, 2033(~6.6 yrs left)· nominal 20-yr term from priority
H03F 1/223H02H 9/046H03F 3/193H03F 2200/489H03F 1/523H01L 27/0255H10D 89/611
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Claims

Abstract

An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 an input device;   a positive supply voltage pad;   an input signal pad;   a ground pad; and   charged-device model protection circuitry configured to protect the input device from electrostatic discharge, wherein the charged-device model protection circuitry comprises a cascode device, and wherein the cascode device is triggered on by a trigger voltage.   
     
     
         2 . The apparatus of  claim 1 , wherein the charged-device model protection circuitry further comprises de-Q circuitry, wherein the de-Q circuitry comprises a resistor and a diode in series, wherein the input device comprises an n-channel transistor, wherein the resistor is coupled to a source of the n-channel transistor, and wherein a cathode of the diode is coupled to a gate of the n-channel transistor. 
     
     
         3 . The apparatus of  claim 2 , further comprising an inductor coupled between the source of the n-channel transistor and the ground pad. 
     
     
         4 . The apparatus of  claim 2 , wherein the de-Q circuitry is configured to direct electrostatic discharge through a +ve diode coupled between the ground pad and the input signal pad. 
     
     
         5 . The apparatus of  claim 2 , wherein the de-Q circuitry is configured to keep a voltage from the gate of the n-channel transistor to the source of the n-channel transistor less than a voltage difference between the input signal pad and a local ground node on the apparatus. 
     
     
         6 . The apparatus of  claim 1 , wherein the cascode device is configured to turn on the input device during −ve electrostatic discharge. 
     
     
         7 . The apparatus of  claim 6 , wherein the cascode device comprises a first n-channel transistor, wherein a gate of the first n-channel transistor is coupled to an RC clamp trigger voltage, and wherein a source of the first n-channel transistor is coupled to a drain of the input device. 
     
     
         8 . The apparatus of  claim 7 , wherein turning on the input device increases a source potential of the input device, protecting a gate-to-source of the input device. 
     
     
         9 . A method for electrostatic discharge protection, comprising:
 detecting a −ve voltage pulse at an input signal pad;   conducting current through a −ve diode coupled between the input signal pad and a local supply node;   steering −ve current to a ground pad via an RC clamp;   turning on a cascode device using an RC clamp trigger voltage from the RC clamp;   turning on an input device using the cascode device; and   maintaining a voltage from a gate of the input device to a source of the input device that is below a failure point for the input device.   
     
     
         10 . The method of  claim 9 , wherein the cascode device comprises a cascode device, and wherein the cascode device turns on the input device during −ve electrostatic discharge. 
     
     
         11 . The method of  claim 10 , wherein the cascode device comprises a first n-channel transistor, wherein a gate of the first n-channel transistor is coupled to the RC clamp trigger voltage, and wherein a source of the first n-channel transistor is coupled to a drain of the input device. 
     
     
         12 . The method of  claim 10 , wherein turning on the input device increases a source potential of the input device, protecting a gate-to-source of the input device. 
     
     
         13 . The method of  claim 9 , further comprising comprising:
 detecting a +ve voltage pulse at a ground pad;   conducting current through a +ve diode coupled between the ground pad and the input signal pad;   generating a voltage drop across a degeneration inductor coupled between the input device and the ground pad; and   limiting current passing from the source of the input device to the gate of the input device using de-Q circuitry.   
     
     
         14 . The method of  claim 13 , wherein the de-Q circuitry comprises a resistor and a diode in series, wherein the input device comprises an n-channel transistor, wherein the resistor is coupled to a source of the n-channel transistor, and wherein a cathode of the diode is coupled to a gate of the n-channel transistor. 
     
     
         15 . The method of  claim 14 , wherein the de-Q circuitry directs electrostatic discharge through the +ve diode. 
     
     
         16 . An apparatus for electrostatic discharge protection, comprising:
 means for detecting a −ve voltage pulse at an input signal pad;   means for conducting current through a −ve diode coupled between the input signal pad and a local supply node;   means for steering −ve current to a ground pad via an RC clamp;   means for turning on a cascode device using an RC clamp trigger voltage from the RC clamp;   means for turning on an input device using the cascode device; and   means for maintaining a voltage from a gate of the input device to a source of the input device that is below a failure point for the input device.   
     
     
         17 . The apparatus of  claim 16 , wherein the cascode device is configured to turn on the input device during −ve electrostatic discharge. 
     
     
         18 . The apparatus of  claim 17 , wherein the cascode device comprises a first re-channel transistor, wherein a gate of the first n-channel transistor is coupled to the RC clamp trigger voltage, and wherein a source of the first n-channel transistor is coupled to a drain of the input device. 
     
     
         19 . The apparatus of  claim 17 , wherein turning on the input device increases a source potential of the input device, protecting a gate-to-source of the input device.

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