Method for performing data management in memory device, associated memory device and controller thereof

Abstract

A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

What is claimed is: 
     
         1 . A method for performing data management in a memory device, the memory device comprising a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory chip, the method comprising:
 receiving a set of data from a host device positioned outside the memory device;   encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix, to generate a partial parity-check code;   performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix, to generate a parity-check code of the set of data, wherein the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and   writing a codeword of the set of data into the non-volatile memory, to allow the memory device to perform error correction when reading the set of data from the non-volatile memory, wherein the codeword comprises the set of data and the parity-check code.   
     
     
         2 . The method of  claim 1 , wherein the host device transmits a writing command to the memory device to request the memory device to store write data; and the method comprises:
 receiving the write data from the host device according to the writing command, wherein the write data comprises a plurality of sets of data, and the plurality of sets of data comprises the set of data;   encoding the plurality of sets of data according to the first sub-matrix to generate a plurality of partial parity-check codes, respectively, wherein the plurality of partial parity-check codes comprises the partial parity-check code;   performing the post-processing upon the plurality of partial parity-check codes according to the predetermined post-processing matrix to generate a plurality of parity-check codes of the plurality of sets of data, respectively, wherein the plurality of parity-check codes comprises the parity-check code; and   writing a plurality of codewords of the write data into the non-volatile memory, to allow the memory device to perform error correction when reading the write data from the non-volatile memory, wherein the plurality of codewords comprises the plurality of sets of data and the plurality of parity-check codes.   
     
     
         3 . The method of  claim 1 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined parity-check matrix is not the predetermined coding transformation matrix. 
     
     
         4 . The method of  claim 1 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined post-processing matrix is not the predetermined coding transformation matrix. 
     
     
         5 . The method of  claim 4 , further comprising:
 generating the parity-check code by performing the post-processing upon the partial parity-check code according to the predetermined post-processing matrix, rather than by performing a multiplication operation upon the set of data and the predetermined coding transformation matrix.   
     
     
         6 . The method of  claim 1 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and an inner product of any row of the predetermined coding transformation matrix and any row of the predetermined parity-check matrix is equal to zero. 
     
     
         7 . The method of  claim 1 , wherein an inner product of the codeword and any row of the predetermined parity-check matrix is equal to zero. 
     
     
         8 . The method of  claim 1 , further comprising:
 reading the codeword from the non-volatile memory, to generate readout data of the codeword;   determining whether the readout data is correct according to the predetermined parity-check matrix; and   when it is determined that the readout data is correct, controlling the memory device to output the set of data carried by the readout data; otherwise, performing error correction according to the readout data to recover the set of data.   
     
     
         9 . The method of  claim 1 , wherein the second sub-matrix is a non-full rank matrix, and the inverse matrix of the transpose matrix of the second sub-matrix does not exist. 
     
     
         10 . The method of  claim 1 , wherein a bit count of the parity-check code is equal to a difference value calculated from a bit count of the codeword minus a bit count of the set of data, and a size of the predetermined parity-check matrix is equal to a product of the difference value and the bit count of the codeword. 
     
     
         11 . The method of  claim 10 , wherein when k and n represent the bit count of the set of data and the bit count of the codeword, respectively, a bit count of the parity-check code is equal to (n−k), and the size of the predetermined parity-check matrix is equal to ((n−k)*n), wherein k and n are positive integers and n>k. 
     
     
         12 . The method of  claim 10 , wherein a size of the first sub-matrix is equal to a product of the difference value and the bit count of the set of data, and a size of the second sub-matrix is equal to a square value of the difference value. 
     
     
         13 . The method of  claim 12 , wherein when k and n represent the bit count of the set of data and the bit count of the codeword, respectively, the bit count of the parity-check code is equal to (n−k), and the size of the predetermined parity-check matrix is equal to ((n−k)*n), wherein k and n are positive integers and n>k; and the size of the first sub-matrix is equal to ((n−k)*k), and the size of the second sub-matrix is equal to ((n−k)*(n−k)). 
     
     
         14 . A memory device, comprising:
 a non-volatile memory, arranged to store information, wherein the non-volatile memory comprises at least one non-volatile memory chip; and   a controller, coupled to the non-volatile memory, the controller arranged to perform data management in the memory device, wherein:
 the controller receives a set of data from a host device positioned outside the memory device; 
 the controller encodes the set of data according to a first sub-matrix of a predetermined parity-check matrix, to generate a partial parity-check code; 
 the controller performs post-processing upon the partial parity-check code according to a predetermined post-processing matrix, to generate a parity-check code of the set of data, wherein the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and 
 the controller writes a codeword of the set of data into the non-volatile memory, to allow the memory device to perform error correction when reading the set of data from the non-volatile memory, wherein the codeword comprises the set of data and the parity-check code. 
   
     
     
         15 . The memory device of  claim 14 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined parity-check matrix is not the predetermined coding transformation matrix. 
     
     
         16 . The memory device of  claim 14 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined post-processing matrix is not the predetermined coding transformation matrix. 
     
     
         17 . The memory device of  claim 16 , wherein the controller generates the parity-check code by performing the post-processing upon the partial parity-check code according to the predetermined post-processing matrix, rather than by performing a multiplication operation upon the set of data and the predetermined coding transformation matrix. 
     
     
         18 . A controller of a memory device, the memory device comprising the controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory chip, the controller comprising:
 a processing circuit, arranged to control the controller to receive a set of data from a host device positioned outside the memory device; and   a data protection circuit, coupled to the processing circuit, the data protection circuit arranged to perform error correction, wherein:
 the data protection circuit encodes the set of data according to a first sub-matrix of a predetermined parity-check matrix, to generate a partial parity-check code; and 
 the data protection circuit performs post-processing upon the partial parity-check code according to a predetermined post-processing matrix, to generate a parity-check code of the set of data, wherein the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; 
   
       wherein the processing circuit controls the controller to write a codeword of the set of data into the non-volatile memory, to allow the memory device to perform error correction when reading the set of data from the non-volatile memory, wherein the codeword comprises the set of data and the parity-check code. 
     
     
         19 . The controller of  claim 18 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined parity-check matrix is not the predetermined coding transformation matrix. 
     
     
         20 . The controller of  claim 18 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined post-processing matrix is not the predetermined coding transformation matrix.