US2018191530A1PendingUtilityA1

Backchannel transmission adaptation

46
Assignee: ALTERA CORPPriority: Sep 22, 2016Filed: Mar 1, 2018Published: Jul 5, 2018
Est. expirySep 22, 2036(~10.2 yrs left)· nominal 20-yr term from priority
H04B 2001/0408H04L 25/03057H04L 25/03343H04B 1/0475H04B 1/04
46
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Receiver circuitry for receiving a data signal includes summation node circuitry that predicts an error value of the received data signal. The receiver circuitry also includes adaptation engine circuitry coupled to the summation node circuitry. The adaptation engine circuitry determines a transmitter adjustment based on the error value and sends a freeze signal to one or more components of the receiver to cause the receiver to continue operating without changing current settings of the one or more components. The receiver circuitry further includes a user interface and sequence controller, coupled to the adaptation engine circuitry, wherein the user interface and sequence controller sends a signal indicative of the transmitter adjustment to the transmitter.

Claims

exact text as granted — not AI-modified
1 . Receiving circuitry for communicating training data to a transmitter, wherein the receiving circuitry is configured to:
 receive a signal from the transmitter;   analyze the signal from the transmitter;   determine an incrementing, decrementing, or holding signal configured to adjust the signal from the transmitter based at least in part on analyzing the signal from the transmitter; and   send the incrementing, decrementing, or holding signal to the transmitter;   wherein the receiving circuitry is at least partially implemented in programmable fabric of a programmable logic device; and   wherein the receiving circuitry is configured to be enabled via an adaptation enable signal sent from the programmable fabric.   
     
     
         2 . The receiving circuitry of  claim 1 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter via a backchannel communicatively coupling the receiving circuitry and the transmitter. 
     
     
         3 . The receiving circuitry of  claim 1 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter via an Ethernet communication link. 
     
     
         4 . The receiving circuitry of  claim 1 , wherein the transmitter comprises an equalizer that is adjusted based at least in part on the incrementing, decrementing, or holding signal. 
     
     
         5 . The receiving circuitry of  claim 1 , wherein the programmable logic device comprises a field-programmable gate array. 
     
     
         6 . The receiving circuitry of  claim 1 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter as training feedback. 
     
     
         7 . The receiving circuitry of  claim 1 , wherein the incrementing, decrementing, or holding signal is configured to reduce signal loss in the signal from the transmitter. 
     
     
         8 . A method for communicating training data to a transmitter, comprising:
 receiving a data signal at a receiver from a transmitter, wherein the receiver is at least partially implemented in programmable fabric of a programmable logic device, wherein the receiver is configured to be enabled via an adaptation enable signal sent from the programmable fabric;   analyzing the data signal from the transmitter;   determining an incrementing, decrementing, or holding signal configured to adjust the signal from the transmitter based at least in part on analyzing the data signal from the transmitter; and   sending the incrementing, decrementing, or holding signal to the transmitter.   
     
     
         9 . The method of  claim 8 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter via a backchannel communicatively coupling the receiver and the transmitter. 
     
     
         10 . The method of  claim 8 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter via an Ethernet communication link. 
     
     
         11 . The method of  claim 8 , wherein the transmitter comprises an equalizer that is adjusted based at least in part on the incrementing, decrementing, or holding signal. 
     
     
         12 . The method of  claim 8 , wherein the programmable logic device comprises a field-programmable gate array. 
     
     
         13 . The method of  claim 8 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter as training feedback. 
     
     
         14 . The method of  claim 8 , wherein the incrementing, decrementing, or holding signal is configured to reduce signal loss in the data signal from the transmitter. 
     
     
         15 . A communication system for communicating training data, comprising:
 a transmitter configured to send a data signal to a receiver; and   the receiver at least partially implemented in programmable fabric of a programmable logic device, wherein the receiver is configured to be enabled via an adaptation enable signal sent from the programmable fabric, wherein the receiver is configured to:
 receive the data signal from the transmitter; 
 analyze the data signal from the transmitter; 
 determine an incrementing, decrementing, or holding signal configured to adjust the signal from the transmitter based at least in part on analyzing the data signal from the transmitter; and 
 send the incrementing, decrementing, or holding signal to the transmitter. 
   
     
     
         16 . The communication system of  claim 15 , comprising a backchannel communicatively coupling the receiver and the transmitter, wherein the receiver is configured to send the incrementing, decrementing, or holding signal to the transmitter via the backchannel. 
     
     
         17 . The communication system of  claim 15 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter via an Ethernet communication link. 
     
     
         18 . The communication system of  claim 15 , wherein the transmitter comprises an equalizer that is adjusted based at least in part on the incrementing, decrementing, or holding signal. 
     
     
         19 . The communication system of  claim 15 , wherein the programmable logic device comprises a field-programmable gate array. 
     
     
         20 . The communication system of  claim 15 , wherein the incrementing, decrementing, or holding signal is sent to the transmitter as training feedback. 
     
     
         21 . A data center system, comprising:
 a transmitter configured to send a data signal to a data processing system via the communication network; and   the data processing system comprising a processor, a memory, and a field programmable gate array (FPGA), wherein the processor is configured to run user programs, wherein the FPGA is configured to enable the processor to connect to the communication network, wherein the receiver is configured to be enabled via an adaptation enable signal sent from the programmable fabric, wherein the receiver is configured to:
 receive the data signal from the transmitter; 
 analyze the data signal from the transmitter; 
 determine an incrementing, decrementing, or holding signal configured to adjust the signal from the transmitter based at least in part on analyzing the data signal from the transmitter; and 
 send the incrementing, decrementing, or holding signal to the transmitter. 
   
     
     
         22 . A system comprising:
 receiving circuitry configured to receive a signal from a transmitter; and   control circuitry configured to:
 receive an enable signal from a circuit programmed in programmable logic fabric of a programmable logic device; and 
 determine an incrementing, decrementing, or holding signal configured to adjust the signal from the transmitter based at least in part on an analysis of the signal from the transmitter and enable signal, wherein the incrementing, decrementing, or holding signal is configured to be sent to the transmitter and cause the transmitter to adjust the signal being sent from the transmitter; 
   wherein the receiving circuitry or the control circuitry, or both, are at least partially implemented in the programmable logic fabric of the programmable logic device.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.