Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

1 - 10 . (canceled) 
     
     
         11 . A semiconductor integrated circuit device comprising a semiconductor chip, the semiconductor chip comprising:
 a core region including logic circuits having semiconductor elements;   an I/O region arranged around the core region;   a plurality of I/O pads formed in the I/O region; and   a plurality of I/O parts formed in the I/O region and disposed along an edge of the semiconductor chip, each of the I/O parts coupled with an associated one of the I/O pads,   the I/O parts each comprising:
 an output buffer block including an output buffer to function as an interface for output of signal to the outside, the output buffer including a first transistor and a second transistor; 
 a logic block configured to control the output buffer; and 
 a pad lead part disposed between the logic block and the first transistor, and coupled to the associated one of the I/O pads, 
   wherein, in each of the I/O parts:
 in plan view, the logic block, the pad lead part, the first transistor and the second transistor are arranged in this order starting from a position closer to a center of the semiconductor chip toward the edge of the semiconductor chip, 
 the pad lead part is coupled with a connection part of a drain terminal of the first transistor and a drain terminal of the second transistor, 
 in the first transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain, 
 in the second transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain. 
   
     
     
         12 . The semiconductor integrated circuit device according to  claim 11 ,
 wherein conductivity of the first transistor is different from conductivity of the second transistor.   
     
     
         13 . The semiconductor integrated circuit device according to  claim 11 ,
 wherein the output buffer block includes a first and a second diode for ESD protection, and   wherein both the first and the second diodes are coupled to the connection part of the drain terminal of the first transistor and the drain terminal of the second transistor.   
     
     
         14 . The semiconductor integrated circuit device according to  claim 13 ,
 wherein the first and the second diodes are arranged between the first transistor and the second transistor.   
     
     
         15 . The semiconductor integrated circuit device according to  claim 13 ,
 wherein the first and the second diodes are arranged between the first transistor and the pad lead part.   
     
     
         16 . The semiconductor integrated circuit device according to  claim 13 ,
 wherein the first and the second diodes are arranged between the logic block and the pad lead part.   
     
     
         17 . The semiconductor integrated circuit device according to  claim 13 ,
 wherein the first diode is arranged between the logic block and the pad lead part, and   wherein the second diode is arranged between the pad lead part and the first transistor.   
     
     
         18 . The semiconductor integrated circuit device according to  claim 11 ,
 wherein the output buffer block further comprises a resistor, and   wherein the pad lead part is coupled with the connection part of the drain terminal of the first transistor and the drain terminal of the second transistor through the resistor.   
     
     
         19 . The semiconductor integrated circuit device according to  claim 18 ,
 wherein the resistor is arranged between the pad lead part and the first transistor.   
     
     
         20 . The semiconductor integrated circuit according to  claim 11 ,
 wherein the I/O pads comprise a plurality of first I/O pads and a plurality of second I/O pads,   wherein each of the first I/O pads is arranged closer to the center of the semiconductor chip than the pad lead part so as to be overlapped with the logic block of a corresponding one of the I/O parts in plan view, and   wherein each of the second I/O pads is arranged closer to the edge of the semiconductor chip than the pad lead part so as to be overlapped with the output buffer block of a corresponding one of the I/O parts in plan view.