Method and apparatus for encoding and decoding packet

Abstract

A method of a transmitter transmitting a packet encoded by applying a coding scheme based on a wireless channel environment to a receiver, and a method of the receiver detecting the coding scheme applied to the encoded packet and decoding the packet, in which the transmitter applies a spreading factor corresponding to the coding scheme to a preamble of the packet, and the receiver decodes the packet by detecting the coding scheme using the preamble.

What is claimed is: 
     
         1 . An operating method of a transmitter, the method comprising:
 generating a preamble;   spreading a SFD (start frame delimiter) based on a bit-to-sequence mapping;   spreading a PHR (physical layer Header) based on the bit-to-sequence mapping;   generating a sequence of chips based on a PSDU(physical service data unit);   concatenating the generated preamble, the spread SFD, the spread PFR, and the generated sequence; and   transmitting, to a receiver, a signal generated based on a result of the concatenating.   
     
     
         2 . The method of  claim 1 , wherein the spreading the SFD comprises spreading 0 in SFD into [0 −1 0 1 1 0 −1 0] and spreading 1 in the SFD into [1 0 −1 0 0 −1 0 1]. 
     
     
         3 . The method of  claim 1 , wherein the spreading the PHR comprises spreading 0 in the PHR into [0 −1 0 1 1 0 −1 0] and spreading 1 in the PHR into [1 0 −1 0 0 −1 0 1]. 
     
     
         4 . The method of  claim 1 , wherein the generated preamble is a ternary base sequence of length 32 chips repeated 8 times. 
     
     
         5 . The method of  claim 4 , wherein the ternary base sequence is [−1 0 −1 0 0 −1 0 −1 1 0 1 0 0 −1 0 1 1 0 1 0 0 −1 0 1 −1 0 1 0 0 1 0 1]. 
     
     
         6 . The method of  claim 1 , wherein the generating the sequence of the chips comprises:
 encoding the PSDU;   interleaving the encoded PSDU;   converting a bit stream comprising a result of the interleaving to a data symbol; and   mapping the data symbol to the sequence of the chips.   
     
     
         7 . An operating method of a receiver, the method comprising:
 receiving a signal from a transmitter; and   processing the signal, wherein the processed signal comprises:   a preamble, a spread SFD (start frame delimiter), a spread PHR (physical layer Header), and a sequence of chips.   
     
     
         8 . The method of  claim 7 , wherein [0 −1 0 1 1 0 −1 0] in the spread SFD corresponds to 0, and [1 0 −1 0 0 −1 0 1] in the spread SFD corresponds to 1. 
     
     
         9 . The method of  claim 7 , wherein [0 −1 0 1 1 0 −1 0] in the spread PHR corresponds to 0, and [1 0 −1 0 0 −1 0 1] in the spread PHR corresponds to 1. 
     
     
         10 . The method of  claim 7 , wherein the preamble is a ternary base sequence of length 32 chips repeated 8 times. 
     
     
         11 . The method of  claim 10 , wherein the ternary base sequence is [1 0 −1 0 0 −1 0 −1 1 0 1 0 0 −1 0 1 1 0 1 0 0 −1 0 1 −1 0 1 0 0 1 0 1]. 
     
     
         12 . A transmitter, comprising:
 a processor configured to generate a preamble, spread a SFD (start frame delimiter) based on a bit-to-sequence mapping, spread a PHR (physical layer Header) based on the bit-to-sequence mapping, generate a sequence of chips based on a PSDU(physical service data unit), and concatenate the generated preamble, the spread SFD, the spread PFR, and the generated sequence; and   a transmitter configured to transmit, to a receiver, a signal generated based on a result of the concatenating.   
     
     
         13 . The transmitter of  claim 12 , wherein the processor is further configured to spread 0 in the SFD into [0 −1 0 1 1 0 −1 0] and spread 1 in the SFD into [1 0 −1 0 0 −1 0 1]. 
     
     
         14 . The transmitter of  claim 12 , wherein the processor is further configured to spread 0 in the PHR into [0 −1 0 1 1 0 −1 0] and spread 1 in the PHR into [1 0 −1 0 0 −1 0 1]. 
     
     
         15 . The transmitter of  claim 12 , wherein the generated preamble is a ternary base sequence of length 32 chips repeated 8 times. 
     
     
         16 . The transmitter of  claim 15 , wherein the ternary base sequence is [1 0 −1 0 0 −1 0 −1 1 0 1 0 0 −1 0 1 1 0 1 0 0 −1 0 1 −1 0 1 0 0 1 0 1]. 
     
     
         17 . The transmitter of  claim 12 , wherein the processor is further configured to:
 encode the PSDU;   interleave the encoded PSDU;   convert a bit stream comprising a result of the interleaving to a data symbol; and   map the data symbol to the sequence of the chips.   
     
     
         18 . A receiver, comprising:
 a receiver configured to receive a signal from a transmitter; and   a processor configured to process the signal, wherein the processed signal comprises:   a preamble, a spread SFD (start frame delimiter), a spread PHR (physical layer Header), and a sequence of chips.   
     
     
         19 . The receiver of  claim 18 , wherein [0 −1 0 1 1 0 −1 0] in the spread SFD corresponds to 0, and [1 0 −1 0 0 −1 0 1] in the spread SFD corresponds to 1. 
     
     
         20 . The receiver of  claim 18 , wherein [0 −1 0 1 1 0 −1 0] in the spread PHR corresponds to 0, and [1 0 −1 0 0 −1 0 1] in the spread PHR corresponds to 1. 
     
     
         21 . The receiver of  claim 18 , wherein the preamble is a ternary base sequence of length 32 chips repeated 8 times. 
     
     
         22 . The receiver of  claim 21 , wherein the ternary base sequence is [1 0 −1 0 0 −1 0 −1 1 0 1 0 0 −1 0 1 1 0 1 0 0 −1 0 1 −1 0 1 0 0 1 0 1].