Data-plane stateful processing units in packet processing pipelines

Abstract

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

1 . A method comprising:
 performing first, second, and third computations at first, second, and third arithmetic logic units (ALUs), respectively;   producing first and second enabling signals based on the third computation, the first enabling signal for enabling the first computation and the second enabling signal for enabling the second computation,   wherein each of the first, second, and third computations is based on a plurality of operands that are selected from (i) a received packet header vector (PHV) and (ii) a state variable that is identified by the PHV.   
     
     
         2 . The method of  claim 1 , wherein different packet header vectors identifies different state variables. 
     
     
         3 . The method of  claim 1 , wherein the stateful variable is retrieved from a memory location having an address that is derived from the packet header vector. 
     
     
         4 . The method of  claim 1 , wherein a packet header vector is derived from information of a packet header. 
     
     
         5 . The method of  claim 4 , wherein the information of the packet header comprises identifiers of a L4 connection. 
     
     
         6 . A programmable stateful processing unit comprising:
 first, second, and third arithmetic logic units (ALUs) for performing first, second, and third computations, respectively;   a predicator for producing first and second enabling signals based on the output of the third computation, the first enabling signal for enabling the first computation and the second enabling signal for enabling the second computation,   wherein each of the first, second, and third computations is based on a plurality of operands that are selected from (i) a received packet header vector and (ii) a state variable that is identified by the packet header vector.   
     
     
         7 . The programmable stateful processing unit of  claim 6 , wherein the third ALU is for determining a condition for enabling the first computation by the first ALU and a condition for enabling the second computation by the second ALU. 
     
     
         8 . The programmable stateful process unit of  claim 6  further comprises fourth, fifth, and sixth ALUs, wherein the fourth ALU is for extending the width of first computation performed by the first ALU, the fifth ALU is for extending the width of second computation performed by the second ALU, and the sixth ALU is for extending the width of third computation performed by the third ALU. 
     
     
         9 . The programmable stateful processing unit of  claim 8 , wherein the predicator is further for enabling the fourth ALU to perform the extended first computation and the fifth ALU to perform the extended second computation. 
     
     
         10 . (canceled) 
     
     
         11 . The programmable stateful processing unit of  claim 6 , wherein the results of the first and second computation are merged to produced a merged ALU output, wherein the first and second enabling signals are respectively for enabling the result of the first and second computations to join the merged ALU output. 
     
     
         12 . The programmable stateful processing unit of  claim 11  further comprises an output multiplexer for producing an output by selecting among (i) the merged ALU output, (ii) the received packet header vector, (iii) the state variable that is identified by the packet header vector, and (iv) the result of the third computation. 
     
     
         13 . The programmable stateful processing unit of  claim 6  further comprises a state variable update multiplexer for producing an update to the identified state variable by selecting among (i) the state variable that is identified by the packet header vector and (ii) the merged ALU output. 
     
     
         14 . A system for performing packet switching operations, the system comprising:
 a plurality of pipeline stages, wherein a first pipeline stage receives incoming packets that are to be processed by each of the pipeline stages, wherein each pipeline stage comprises a set of programmable stateful processing units (DSPU), each DSPU comprising:   first, second, and third arithmetic logic units (ALUs) for performing first, second, and third computations, respectively;   a predicator for producing first and second enabling signals based on the output of the third computation, the first enabling signal for enabling the first computation and the second enabling signal for enabling the second computation,   wherein each of the first, second, and third computations is based on a plurality of operands that are selected from (i) a received packet header vector (PHV) and (ii) a state variable that is identified by the packet header vector.   
     
     
         15 . The system of  claim 14 , wherein each pipeline stage is a match-action stage further comprising a match table and an action engine, wherein the match table is for matching an incoming PHV against a set of rules and for indicating the result of the matching, wherein the action engine performs an action based on said result of the matching and an output of the a DSPU in the pipeline stage. 
     
     
         16 . The system of  claim 14 , wherein each DSPU retrieves its state variables from a memory location having an address that is derived from its received packet header vector. 
     
     
         17 . The system of  claim 14 , wherein a packet header vector is derived from information of a packet header. 
     
     
         18 . The system of  claim 17 , wherein the information of the packet header comprises identifiers of a L4 connection. 
     
     
         19 . The system of  claim 14 , wherein the third ALU is for determining a condition for enabling the first computation by the first ALU and a condition for enabling the second computation by the second ALU.