Semiconductor device

Abstract

The semiconductor devise includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor device comprising:
 a first inverter; and   a second inverter coupled to the first inverter in series,   wherein the first inverter includes a first p-channel transistor and a first n-channel transistor,   the second inverter includes a second p-channel transistor and a second n-channel transistor,   the first p-channel transistor includes:
 a plurality of first sources formed in a plurality of first projection semiconductor layers extending along a first direction; 
 a plurality of first drains formed in the plurality of first projection semiconductor layers; and 
 a plurality of first gates formed by a first gate wiring coupled to the plurality of first projection semiconductor layers and extending along a second direction perpendicular to the first direction, 
   a first local connection wiring extends along the second direction and is coupled to the plurality of first sources,   a second local connection wiring extends along the second direction and is coupled to the plurality of first drains,   the first gate wiring is arranged between the first local connection wiring and the second local connection wiring in plan view,   the first n-channel transistor includes:
 a plurality of second sources formed in a plurality of second projection semiconductor layers extending along the first direction; 
 a plurality of second drains formed in the plurality of second projection semiconductor layers; and 
 a plurality of second gates formed by the first gate wiring coupled to the plurality of second projection semiconductor layers, 
   a third local connection wiring extends along the second direction and is coupled to the plurality of second sources;   a fourth local connection wiring extends along the second direction and is coupled to the plurality of second drains;   the first gate wiring is arranged between the third local connection wiring and the fourth local connection wiring in plan view;   the second p-channel transistor includes:
 a third source formed in a third projection semiconductor layer extending along the first direction; 
 a third drain formed in the third projection semiconductor layer; and 
 a third gate formed by a second gate wiring coupled to the third projection semiconductor layer and extending along the second direction; 
   the first local connection wiring is coupled to the third source,   a fifth local connection wiring extends along the second direction and is coupled to the third drain,   the second gate wiring is arranged between the first local connection wiring and the fifth local connection wiring in plan view,   the second n-channel transistor includes:
 a fourth source formed in a fourth projection semiconductor layer extending along the first direction; 
 a fourth drain formed in the fourth projection semiconductor layer; and 
 a fourth gate formed by the second gate wiring coupled to the fourth projection semiconductor layer, 
   the third local connection wiring is coupled to the fourth source,   a sixth local connection wiring extends along the second direction and is coupled to the fourth drain,   the second gate wiring is arranged between the third local connection wiring and the sixth local connection wiring in plan view,   the fifth and sixth local connection wirings are coupled to the first gate wiring for coupling an output node of the second inverter to an input node of the first inverter,   the second local connection wiring is coupled with the fourth local connection wiring for forming an output node of the first inverter,   the first and second gate wirings and the first, second, third, fourth, fifth and sixth local connection wirings are arranged in a same layer,   a number of the third projection semiconductor layer is less than a number of the first projection semiconductor layers, and   a number of the fourth projection semiconductor layer is less than a number of the second projection semiconductor layers.   
     
     
         21 . The semiconductor device according to  claim 20 , further comprising:
 a first power wiring coupled to the first local connection wiring and arranged over the first local connection wiring; and   a second power wiring coupled to the third local connection wiring and arranged over the third local connection wiring.   
     
     
         22 . The semiconductor device according to  claim 20 , wherein the fifth local connection wiring is coupled to the sixth local connection wiring via a first wiring arranged over the fifth and sixth local connection wirings. 
     
     
         23 . The semiconductor device according to  claim 20 , wherein the second local connection wiring is coupled to the fourth local connection wiring via a second wiring arranged over the second and fourth local connection wirings. 
     
     
         24 . The semiconductor device according to  claim 20 , further comprising:
 a first dummy gate wiring arranged next to the second and fourth local connection wirings,   wherein the first dummy gate wiring is electrically floating.   
     
     
         25 . The semiconductor device according to  claim 24 , further comprising:
 a second dummy gate wiring arranged next to the second and fourth local connection wirings,   wherein the second dummy gate electrode is electrically floating.   
     
     
         26 . The semiconductor device according to  claim 24 ,
 wherein the third projection semiconductor layer continues to one of the plurality of first projection semiconductor layers, and   wherein the fourth projection semiconductor layer continues to one of the plurality of second projection semiconductor layers.   
     
     
         27 . The semiconductor device according to  claim 26 ,
 wherein another of the plurality of first projection semiconductor layers is in contact with the second gate wiring, and   wherein another of the plurality of second projection semiconductor layers is in contact with the second gate wiring.   
     
     
         28 . The semiconductor device according to  claim 20 , wherein a first length, along the second direction, between a portion of the fifth local connection wiring in contact with the third projection semiconductor layer close to the fourth projection semiconductor layer and an end portion of the fifth local connection wiring close to the fourth projection semiconductor layer is greater than a second length, along the second direction, between a portion of the second local connection wiring in contact with one of the first projection semiconductor layers close to the second projection semiconductor layers and an end portion of the second local connection wiring close to the second projection semiconductor layers. 
     
     
         29 . The semiconductor device according to  claim 28 , wherein a third length, along the second direction, between a portion of the sixth local connection wiring in contact with the fourth projection semiconductor layer close to the third projection semiconductor layer and an end portion of the sixth local connection wiring close to the third projection semiconductor layer is greater than a fourth length, along the second direction, between a portion of the fourth local connection wiring in contact with one of the second projection semiconductor layers close to the first projection semiconductor layers and an end portion of the fourth local connection wiring close to the first projection semiconductor layers.