Integrated circuit layout design methodology with process variation bands

Abstract

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

1 - 12 . (canceled) 
     
     
         13 . A system for designing and verifying the circuit designs to be created on a wafer by a photolithographic process, the system comprising:
 at least one processor;   at least one computer-readable storage device coupled to the at least one processor and storing instructions for tools that when executed by the at least one processor, cause the processor to perform a method, the tools comprising:
 a circuit design tool that causes the system to define the placement of circuit objects in a layout in order to perform desired circuit functions; 
   a verification tool that causes the system to determine possible variations in a way in which the objects will be printed on a wafer as a result of variations in the photolithographic process; and   a rule checker that causes the system to compare the possible variations in the objects to one or more design rules to determine one or more rule violations that are marked to be corrected with the circuit design tool.   
     
     
         14 . The system of  claim 13 , wherein the verification tool further causes the system to determine the possible variations by using a process model to simulate the variations. 
     
     
         15 - 34 . (canceled) 
     
     
         35 . The system of  claim 13 , wherein the comparing comprises calculating one or more of an area, perimeter, or length associated with the possible variations. 
     
     
         36 . The system of  claim 13 , wherein the possible variations are determined by convolving the circuit objects with distribution functions of process variables. 
     
     
         37 . The system of  claim 13 , wherein the possible variations are determined by calculating images of the circuit objects with varying process conditions. 
     
     
         38 . The system of  claim 13 , wherein the placement of a first one of the circuit objects is defined at least in part by defining an area of interest for the first circuit object; and the comparing comprises comparing the possible variations for the first object to the defined area of interest to verify if the object will be created correctly on the wafer. 
     
     
         39 . The system of  claim 13 , wherein the rule checker further causes the system to output the verified circuit design after the marked rule violations have been corrected. 
     
     
         40 . The system of  claim 39 , further comprising a mask writing tool configured to receive the verified circuit design over a communication link; wherein the mask writing tool further causes the system to produce one or more masks or reticles. 
     
     
         41 . A computer-implemented method for designing and verifying the circuit designs to be created on a wafer by a photolithographic process, the method comprising:
 defining placement of circuit objects in a layout;   determining possible variations in a way in which the objects will be printed on a wafer as a result of variations in the photolithographic process; and   using a design rule check to compare possible variations in the objects with one or more computer-readable design rules to determine one or more rule violations that are marked to be corrected with the circuit design tool.   
     
     
         42 . The method of  claim 41 , wherein the determining comprises using a process model to simulate the variations. 
     
     
         43 . The method of  claim 41 , wherein the comparing comprises calculating one or more of an area, perimeter, or length associated with the possible variations. 
     
     
         44 . The method of  claim 41 , wherein the determining comprises convolving the circuit objects with distribution functions of process variables. 
     
     
         45 . The method of  claim 41 , wherein the determining comprises calculating images of the circuit objects with varying process conditions. 
     
     
         46 . The method of  claim 41 , wherein the defining action comprises defining an area of interest for a first one of the circuit objects; and the comparing action comprises comparing the possible variations for the first circuit object to the defined area of interest to verify if the object will be created correctly on the wafer. 
     
     
         47 . The method of  claim 41 , further comprising outputting the verified circuit design after the marked rule violations have been corrected. 
     
     
         48 . The method of  claim 47 , further comprising, with a mask writing tool:
 receiving the verified circuit design over a communication link; and   producing one or more masks or reticles for the verified circuit design.   
     
     
         49 . One or more computer-readable storage devices storing instructions that, when executed by one or more processors, cause the processors to perform a method for designing and verifying a layout for an integrated circuit design to be created on a wafer by a photolithographic process, the method comprising:
 determining, with a verification tool, possible variations in a way in which circuit objects in the layout will be printed on a wafer as a result of variations in the photolithographic process; and   comparing the possible variations in the objects to one or more design rules to determine one or more rule violations that are marked to be corrected with the circuit design tool.   
     
     
         50 . The computer-readable storage devices of  claim 49 , wherein the determining comprises using a process model to simulate the variations. 
     
     
         51 . The computer-readable storage devices of  claim 41 , wherein the determining comprises calculating images of the circuit objects with varying process conditions. 
     
     
         52 . The computer-readable storage devices of  claim 41 , wherein the method further comprises outputting the verified circuit design after the marked rule violations have been corrected.