Semiconductor memory apparatus and operating method

Abstract

A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

1 - 10 . (canceled) 
     
     
         11 . A method for operating a semiconductor memory apparatus, comprising:
 activating a first mat by enabling both a first bit line and a first word line included in the first mat;   in a second mat including a second bit line and a second word line, enabling only the second bit line; and   generating an output data by sensing a voltage or current difference between the enabled first and second bit lines.   
     
     
         12 . The method according to  claim 11 , wherein the enabling of only the second bit line comprises enabling the second bit line included in the second mat in response to a column address indicating the first bit line. 
     
     
         13 . The method according to  claim 11 , wherein the enabling of the second bit line included in the second mat uses a state machine which operates in response to the column address. 
     
     
         14 . The method according to  claim 11 , wherein the first and second mats are adjacent to each other and the generating of the output data uses a sense amplifier to which the first and second bit lines are coupled. 
     
     
         15 . A semiconductor memory apparatus including first and second mats, the semiconductor memory apparatus comprising:
 a decoding unit configured to enable first and second select signals in response to a column address indicating one of bit lines respectively included in the first and second mats;   a driving unit configured to activate the bit line of the first mat in response to one of the enabled first and second select signals, and to activate the bit line of the second mat in response to the other one of the enabled first and second select signals; and   a sensing unit configured to sense difference in voltages or currents between the activated bit lines respectively included in the first and second mats.