Method for Separating Chips from a Wafer

Abstract

The invention relates to a method for producing chips ( 13 ) by dividing a wafer along dividing lines ( 11, 12 ) defining dimensions of the chip, wherein a focus ( 18 ) of a preferably pulsed laser radiation ( 16 ) is moved along the dividing lines on a first and at least a second path ( 25, 26 ) within the wafer body, wherein the laser radiation is applied to the wafer from a rear side ( 17 ) of the wafer, and the power density for producing the defects ( 28 ) on the first path ( 25 ) is lower than the power density for producing the defects ( 29 ) on the second path ( 26 ), and/or the number of defects on the first path is smaller than the number of defects on the second path.

What is claimed is: 
     
         1 . An electronic device comprising:
 a semiconductor body having a height, a front side, a rear side, and at least a lateral surface between the front side and the rear side;   a functional layer formed on the front side of the semiconductor body,   wherein the semiconductor body comprises at least two path marks on the lateral surface,   wherein the two path marks are generated by defects in the lateral surface along the paths,   wherein the first path mark is arranged between the functional layer and the second path mark,   wherein the first path mark is disposed in the upper 15 to 25% of the height, relative to the functional layer.   
     
     
         2 . A device as in  claim 1   wherein the lateral surface exhibits a lower level of roughness in a surface area between the first path mark and the front side as compared to a surface area between the first path mark and the second path mark.   
     
     
         3 . A device as in  claim 1   wherein the number of defects along the first path mark is smaller than the number of defects along the second path mark.   
     
     
         4 . A device as in  claim 1   wherein the second path mark runs adjacent to or on a center line of the lateral surface.   
     
     
         5 . A device as in  claim 1  further comprising
 a third path mark in the lateral surface at a distance from the rear side, wherein the distance is larger than 10% of the height. 
 
     
     
         6 . A device as in  claim 1   wherein the defects are formed as a result of a partial melting of the semiconductor body.   
     
     
         7 . A device as in  claim 1   wherein the device is separated by a material fracture in the lateral surface along the two path marks.   
     
     
         8 . A device as in  claim 1   wherein the first path mark forms a barrier against crack propagation beyond the first path mark in the direction of the functional layer,   wherein the barrier is characterized by a reduction of cracks across the first path mark.   
     
     
         9 . A device as in  claim 1   wherein a falling gradient of internal stresses is formed from the second path mark to the first path mark, with the internal stresses induced by the defects in the lateral surface, or   wherein the falling stress gradient is formed by a lower power density used to produce defects on the first path mark and a higher power density used to produce defects on the second path mark, wherein the internal stresses is induced along the first and second path marks by the defects.   
     
     
         10 . An electronic device comprising:
 a semiconductor body of silicon having a height, a front side, a rear side, and at least a lateral surface between the front side and the rear side;   a functional layer formed on the front side of the semiconductor body,   wherein the semiconductor body comprises at least two path marks on the lateral surface,   wherein the first path mark is arranged between the functional layer and the second path mark,   wherein the two path marks are generated by defects in the lateral surface along the path marks,   wherein the first path mark forms a barrier against crack propagation beyond the first path mark in the direction of the functional layer,   wherein the barrier is characterized by a reduction of cracks across the first path mark.   
     
     
         11 . A device as in  claim 10   wherein a portion of the lateral surface between the first path mark and the second path mark comprises micro cracks.   wherein the micro cracks do not propagate beyond the first path mark.   
     
     
         12 . A device as in  claim 10   wherein a portion of the lateral surface between the first path mark and the second path mark comprises Wallner lines which extend as far as to the first path mark.   
     
     
         13 . A device as in  claim 10  further comprising
 a third path mark in the lateral surface between the center line and the rear side of the semiconductor body. 
 
     
     
         14 . A device as in  claim 10   wherein a falling gradient of internal stresses is formed from the second path mark to the first path mark, with the internal stresses induced by the defects in the lateral surface,   wherein the falling stress gradient is formed by a lower power density used to produce defects on the first path mark and a higher power density used to produce defects on the second path mark, wherein the internal stresses induced along the first and second path marks by the defects.   
     
     
         15 . An electronic device comprising:
 a semiconductor body of silicon having a height, a front side, a rear side, and at least a lateral surface between the front side and the rear side;   a functional layer formed on the front side of the semiconductor body,   wherein the semiconductor body comprises at least two path marks on the lateral surface,   wherein the first path mark is arranged between the functional layer and the second path mark,   wherein the two path marks are generated by defects in the lateral surface along the path marks,   wherein a falling gradient of internal stresses is formed from the second path mark to the first path mark, wherein the internal stresses are induced by the defects.   
     
     
         16 . A device as in  claim 15  further comprising
 a third path mark in the lateral surface between the center line and the rear side of the semiconductor body. 
 
     
     
         17 . A device as in  claim 15   wherein the defects comprises a partial melting of the semiconductor body.   
     
     
         18 . A device as in  claim 15   wherein the number of defects along the first path mark is smaller than the number of defects along the second path mark.   
     
     
         19 . A device as in  claim 15   wherein a portion of the lateral surface between the first path mark and the second path mark comprises micro cracks.   
     
     
         20 . A device as in  claim 15   wherein there is a reduction of cracks across the first path mark in the lateral surface.