Driver Interface Methods and Apparatus for Switch-Mode Power Converters, Switch-Mode Power Amplifiers, and Other Switch-Based Circuits

Abstract

A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.

What is claimed is: 
     
         1 . A method of interfacing a gate driver circuit to a switch-based circuit, comprising:
 receiving an input duty cycle varying or pulse width varying bi-level drive signal V drive ;   removing a direct current (DC) component from the input duty cycle varying or pulse width varying bi-level drive signal V drive  to produce a level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′;   clamping the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ between two levels using a first diode or first series of diodes and a second diode or second series of diodes connected in parallel with the first diode or first series of diodes but with opposing polarity;   applying the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ to a gate of a field-effect transistor (FET) in the switch-based circuit; and   switching the FET between ON and OFF states in response to the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′,   wherein clamping the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ between two levels comprises:   conducting said first diode or first series of diodes every cycle of the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ to establish and maintain a high drive voltage level V H  of the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ within a required acceptable input high-level range of the switch-based circuit over all cycles and irrespective of any changes in the duty cycle of the input duty cycle varying or pulse width varying bi-level drive signal V drive , and   conducting said second diode or second series of diodes every cycle of the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ to establish and maintain a low drive voltage level V L  of the level-adjusted duty cycle varying or pulse width varying bi-level drive signal V drive ′ within a required acceptable input low-level range of the switch-based circuit over all cycles and irrespective of any changes in the duty cycle of the input duty cycle varying or pulse width varying bi-level drive signal V drive .   
     
     
         2 . The method of  claim 1 , further comprising maintaining a source of the FET at ground potential or at a fixed reference voltage. 
     
     
         3 . The method of  claim 2 , wherein the FET is a low-side FET of a switch-mode power converter or a switch-mode power amplifier. 
     
     
         4 . The method of  claim 1 , wherein the FET is a depletion mode control FET, which when switched ON serves as a current path along which a gate capacitor of a high-side FET of a switch-mode power converter or switch-mode power amplifier can discharge in order to switch the high-side FET OFF. 
     
     
         5 . The method of  claim 1 , wherein removing the DC component from the input duty cycle varying or pulse width varying bi-level drive signal V drive  comprises applying the input duty cycle varying or pulse width varying bi-level drive signal V drive  to a transformer, and wherein the FET is the high-side FET of a switch-mode power converter or switch-mode power amplifier. 
     
     
         6 . A driver interface for a switch-based circuit, comprising:
 a first series of diodes including one or more diodes configured to clamp a high drive voltage level of a duty cycle varying or pulse width varying bi-level gate-source voltage waveform applied across the gate-source terminals of a field-effect transistor (FET) in the switch-based circuit to a voltage greater than a threshold voltage of the FET; and   a second series of diodes including one or more diodes connected in parallel with the first diode or the first series of diodes but with an opposing polarity, said second series of diodes configured to clamp a low drive voltage level of the duty cycle varying or pulse width varying bi-level gate-source voltage waveform to a voltage less than the FET's threshold voltage,   wherein the first series of diodes conducts every cycle and maintains the high drive voltage level within a required acceptable input high-level range of the switch-based circuit over all cycles, irrespective of changes of the duty cycle or pulse widths of the duty cycle varying or pulse width varying bi-level gate-source voltage waveform, and the second series of diodes conducts every cycle and maintains the low drive voltage level within a required acceptable input low-level range of the switch-based circuit over all cycles, irrespective of changes of the duty cycle or pulse widths of the duty cycle varying or pulse width varying bi-level gate-source voltage waveform.   
     
     
         7 . The driver interface of  claim 6 , wherein:
 the first series of diodes has a cathode that is coupled to or configured to be coupled to a first bias voltage, and   the second series of diodes has an anode that is coupled to or configured to be coupled to a second bias voltage different than the first bias voltage.   
     
     
         8 . The driver interface of  claim 6 , further comprising
 a transformer having a primary winding configured to receive an input gate drive signal and a secondary winding disposed in series with the parallel-connected first series of diodes and second series of diodes; and   a capacitor configured in series with the secondary winding of the transformer.   
     
     
         9 . The driver interface of  claim 8 , wherein:
 the switch-based circuit comprises a half-bridge of a switch-mode power converter or a switching stage of a switch-mode amplifier,   the FET is a high-side FET of the half-bridge or switching stage, and   the circuit formed by the secondary winding of the transformer, the first series of diodes, the second series of diodes, and the capacitor floats with respect to the output of the half-bridge or switching stage and does not share a ground reference in common with the half-bridge or switching stage.