Display panel

Abstract

A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

What is claimed is: 
     
         1 . A display panel, comprising:
 a substrate, having a display area and a peripheral area;   a plurality of pixels, disposed on the display area;   a plurality of scan lines, disposed on the substrate and respectively coupled to the corresponding pixels, the scan lines extending from the display area to the peripheral area;   a pull-down control circuit, disposed on the peripheral area, the pull-down control circuit receiving a plurality of clock signals and having a plurality of pull-down units to provide a plurality of first pull-down signals; and   a gate driving circuit, disposed on the peripheral area and having a plurality of shift registers, wherein the shift registers are coupled to the scan lines to provide a plurality of gate driving signals, the shift registers are coupled to the pull-down control circuit to receive the first pull-down signals, the shift registers enable the gate driving signals in sequence according to the clock signals, and the shift registers pull down the gate driving signals in sequence according to the first pull-down signals, respectively,   wherein the pull-down control circuit and the gate driving circuit are arranged along a side of the display area.   
     
     
         2 . The display panel as claimed in  claim 1 , wherein enabling periods of the clock signals partially overlap and are different from one another. 
     
     
         3 . The display panel as claimed in  claim 1 , wherein each of the shift registers comprises:
 a pre-charge unit for pre-charging an internal voltage;   a voltage push-up unit, coupled to the pre-charge unit for pushing up i th  gate driving signal of the gate driving signals according to the internal voltage, wherein i is a positive integer; and   a voltage pull-down unit, receiving the corresponding first pull-down signal for pulling down the internal voltage and the i th  gate driving signal according to the corresponding first pull-down signal.   
     
     
         4 . The display panel as claimed in  claim 3 , wherein the pre-charge unit comprises:
 a first transistor, wherein a first terminal of the first transistor receives a forward scanning voltage, a second terminal of the first transistor is coupled to the internal voltage, and a control terminal of the first transistor receives (i−1) th  gate driving signal of the gate driving signals or a start signal; and   a second transistor, wherein a first terminal of the second transistor receives a reverse scanning voltage, a second terminal of the second transistor is coupled to the internal voltage, and a control terminal of the second transistor receives (i+1) th  gate driving signal of the gate driving signals.   
     
     
         5 . The display panel as claimed in  claim 3 , wherein the voltage pull-down unit comprises:
 a third transistor, wherein a first terminal of the third transistor is coupled to the internal voltage, a second terminal of the third transistor receives a gate low voltage, and a control terminal of the third transistor receives the corresponding first pull-down signal; and   a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the i th  gate driving signal, a second terminal of the fourth transistor receives the gate low voltage, and a control terminal of the fourth transistor receives the corresponding first pull-down signal.   
     
     
         6 . The display panel as claimed in  claim 3 , wherein the voltage push-up unit comprises:
 a fifth transistor, wherein a first terminal of the fifth transistor receives a first clock signal of the clock signals, a second terminal of the fifth transistor is coupled to the i th  gate driving signal, and a control terminal of the fifth transistor receives the internal voltage; and   a first capacitor, coupled between the second terminal and the control terminal of the fifth transistor.   
     
     
         7 . The display panel as claimed in  claim 6 , wherein each of the pull-down units comprises:
 a sixth transistor, wherein a first terminal of the sixth transistor receives a forward scanning voltage, a second terminal of the sixth transistor is coupled to the corresponding first pull-down signal, and a control terminal of the sixth transistor receives a second clock signal of the clock signals; and   a seventh transistor, wherein a first terminal of the seventh transistor receives a reverse scanning voltage, a second terminal of the seventh transistor is coupled to the corresponding first pull-down signal, and a control terminal of the seventh transistor receives a third clock signal of the clock signals.   
     
     
         8 . The display panel as claimed in  claim 7 , wherein an enabling period of the first clock signal and an enabling period of the second clock signal partially overlap, the enabling period of the first clock signal and an enabling period of the third clock signal partially overlap, a phase of the first clock signal leads a phase of the second clock signal, and the phase of the first clock signal lags a phase of the third clock signal. 
     
     
         9 . The display panel as claimed in  claim 7 , wherein the forward scanning voltage is one of a gate high voltage and a gate low voltage, and the reverse scanning voltage is the other one of the gate high voltage and the gate low voltage. 
     
     
         10 . The display panel as claimed in  claim 6 , wherein each of the pull-down units comprises:
 an eighth transistor, wherein a first terminal and a control terminal of the eighth transistor receive a fourth clock signal of the clock signals, and a second terminal of the eighth transistor is coupled to the corresponding first pull-down signal.   
     
     
         11 . The display panel as claimed in  claim 10 , wherein an enabling period of the first clock signal and an enabling period of the fourth clock signal partially overlap, and a phase of the first clock signal leads a phase of the fourth clock signal. 
     
     
         12 . The display panel as claimed in  claim 3 , wherein the pre-charge unit comprises:
 a ninth transistor, wherein a first terminal and a control terminal of the ninth transistor receive (i−1) th  gate driving signal of the gate driving signals, and a second terminal of the ninth transistor is coupled to the internal voltage.